Modular FPGA Miner Hardware Design Development

[senseless]

where to get the ISE Logic edition for a reasonable price (<<1kEUR)?

I've been wondering about their pricing model. One guy in a previous post on this thread was saying there is a yearly fee associated with the software? I've been looking online and haven't been able to verify that claim. There are used versions of the Design Suite (12.1 and 12.3) on ebay for few hundred to 1K.

[fizzisist]

[...]
I might get the board just to get a start with FPGA's, but otherwise it is reassuring that we seem to be on the right track complexity and price-wise.

I would, too, if there wasn't the issue with the software: where to get the ISE Logic edition for a reasonable price (<<1kEUR)?

Isn't this still a problem for our design? I thought we will have to rely on people like me who have an ISE license.

[Olaf.Mandel]

[...]
I would [buy a board], too, if there wasn't the issue with the software: where to get the ISE Logic edition for a reasonable price (<<1kEUR)?

Isn't this still a problem for our design? I thought we will have to rely on people like me who have an ISE license.

It is, but if I don't have the software, I concentrate on the hardware. If I had the software, I might dabble a bit in both.

[grid]

I would, too, if there wasn't the issue with the software: where to get the ISE Logic edition for a reasonable price (<<1kEUR)?

Yeah, that's the main issue here. There's always the 30-day trial to start with. I was actually going to write Xilinx and see if they are willing to contribute some ISE licenses to this project, provided that it is properly open sourced. I wouldn't write them however until we have a clearly stated project license type in the first post, or a webpage. Xilinx seems to support educational and non-commercial institutions, I was able to find some references to Xilinx license donations.

[TheSeven]

[...]
I also agree the MSP should be powered by the power solution of the fpga.The level shifters would add adtitional parts and complicate things so we my use this in another version.
[...]

Careful: you are killing one of the original features here: if the MSP is not powered from the USB connector, then it cannot enable or disable the power for the FPGAs. This was (at least for me) an important feature. And I don't see the problem, actually: you just need an additional small switcher that hangs on the USB power pin and outputs 2.5V. No reason to talk about level shifters or anything.

So you just call for an additional littel 2.5 V source just for the MCU in order to make it independent from the FPGA power supply? If thats teh case you are cerrtainly right. I thought you wanted to use an centrall power supply controler in addition.
Sorry for the misunderstanding.

Seriously, a switcher is overkill for this. Its quiescent current will be higher than what an LDO would waste.
Being able to switch off the MSP power doesn't make any sense to me, and I'm not sure whether it's neccessary to be able to switch off the FPGAs.
Does someone have information on how much power they draw if one puts them into programming mode, or whether there's even a dedicated shutdown mode for them?
Is it allowed for the 2.5V rail to be on but the 1.2V rail to be off? If yes, how much current would the FPGA draw in that case?

[Olaf.Mandel]

[...]
Seriously, a switcher is overkill for this. Its quiescent current will be higher than what an LDO would waste.
Being able to switch off the MSP power doesn't make any sense to me, and I'm not sure whether it's neccessary to be able to switch off the FPGAs.
Does someone have information on how much power they draw if one puts them into programming mode, or whether there's even a dedicated shutdown mode for them?
Is it allowed for the 2.5V rail to be on but the 1.2V rail to be off? If yes, how much current would the FPGA draw in that case?

Why switch off the MSP? That makes no sense to me, too. The FPGA has several stages of power saving (a little bit explained in UG394):

Name	Power consumption
Normal operation	?? 7,6W ??
Suspend	?? 4.5W / 0.06W
Reset	0.1W
Off	0W

In the above table, I am especially unhappy about the Suspend mode power consumption: All I can find is a reduction of current by 40%, but is that from normal operational levels or from reset levels?
I don't remember seeing anything explicitly written about VCCINT being off, but I would guess this is actually deleting the configuration.

[O_Shovah]

I added the USB pullup resistor and the external 25 mhz clock source to my MSP setup.
(Standby# pin of clock source is left floating to provide constant clock output)
Just uploaded it.

Please check on possible errors.

[li_gangyi]

I can add a LDO to power the MSP430 if you guys think the hibernation mode on the FPGA is critical, I don't think leaving the Vccaux on all the time while the device is hibernating is a good engineering practice. Only Xilinx can answer if that's a good long term strategy, because it seems like it might work, since you're holding the FPGA from turning on.

The next best thing (instead of switching off the PSUs as well), is to just put the FPGA into what's know as the "Quiescent Current Level" stage, UG394 describes more of this.

O_shovah: nice work, I'll add the MSP in later into the combined board we have now.

[TheSeven]

I don't remember seeing anything explicitly written about VCCINT being off, but I would guess this is actually deleting the configuration.

As long as it doesn't destroy the FPGA and doesn't draw excessive power on 2.5V, this should be fine. If we would completely power it down, it would delete its configuration as well.

But yeah, the reset 0.1W look good. Does it even make sense to shut down the PSU in this case? I'd guess that an idle dual-FPGA DIMM (just the MSP running) could be brought down to ~2W (mostly switcher quiescent current) that way, which sounds OK to me, if we can save an additional 2.5V rail that way.

[O_Shovah]

Just to backcheck this.
I am currently using the MSP430F5504 in my layouts.
Is this one suffiecient or do we want to use a 552x model ?

I that case i would have to change some parts of the routing. 

[phillipsjk]

As long as it doesn't destroy the FPGA and doesn't draw excessive power on 2.5V, this should be fine. If we would completely power it down, it would delete its configuration as well.

But yeah, the reset 0.1W look good. Does it even make sense to shut down the PSU in this case? I'd guess that an idle dual-FPGA DIMM (just the MSP running) could be brought down to ~2W (mostly switcher quiescent current) that way, which sounds OK to me, if we can save an additional 2.5V rail that way.

Remember: if all the modules on the motherboard are shut-down (but drawing ~2W each), it is possible for the motherboard logic to turn off the ATX power supply. That is that only logic that needs to run off of 5V. Sorry for the confusion.

[pusle]

About the ISE issue...

I have some contact with Xilinx through work and their business model is selling chips, not software.
As long as it doesn't cost them anything in support/FAE they could not care less where you got your ISE from.

version 13.1 is "out" btw.



About the pcb board layout:

Noise coming  from the feedback pin is a non issue as it's very high impedance compared to the main rail.
The ripple from the switcher and the noise from the FPGA are all already on the VCCINT and dwarfing any other contribution.

When you draw 5 amps you'll be surprised how easily you get lots of mV droop and the FPGA needs
tight tolerance for the core supply. Feedback from near/under the fpga is the best way.

But you should put the divider resistors close to the switching power as li_gangyi  mentioned.


Layer 2 for gnd is because it gives the least inductance for the GND via's.
Same reason for using layer 3 for VCCINT.
Layer choices isn't that critical, but having proper power planes, especially for Gnd IS important.
Sure lots of times the most crazy routing works, but it's best to do what you can to not end up
with a board that behaves in "mysterious ways" 

Could you please give me a link so I can  have a look at the pcb file?

[fizzisist]

pusle, thanks for your comments. I agree with everything you said, including about the Xilinx licensing. If you're a student, you can likely get a free license because they know it will likely mean more chips sold in the future.

Please send a PM to O_Shovah to get access to our shared Dropbox folder.

[Olaf.Mandel]

I uploaded a new version of the schematic, board and PDF+PNG to github. Couldn't upload to dropbox for some weird reason (upgrade to newest Flash?, worked yesterday).

Changes:

• VCCINT is now split into two signals VCCINT0 and VCCINT1 for the two different FPGAs
• VCCAUX is gone, merged with VCCIO
• Layer 2 contains no polygon anymore
• The different FPGAs are spaced further apart, polygons no longer touching
• The termination resistors are folded to the back, reducing the size by half

TODO:

• Unfold the bus to not have several signals on top of each other
• Merge with PSU (again) and MCU

I did this before pusle posted his more detailed explanation. Can you actually look at the file from github and say how bad you think this is?

Also: can someone copy the files to dropbox, because I cannot.

[sirky]

Hey guys,

In case you haven't seen anything about it yet, you might want to read this:

http://forum.bitcoin.org/index.php?topic=29696.msg383806#msg383806

I see TheSeven has talked to this guy in the past on the boards, but I just thought it may be interesting for you all to look at.

Carry on, and keep up the good work!

[O_Shovah]

To things form my side.

@ pulse: If the email adress shown in the forum is valid you should be invited to the dropboxfolder by now.


Regarding my MSP schematic: It seems i missed something on the usb connection side on wich somebody may please have a look.

In addition there is an additional clk in and output (Xin and Xout). Im not shure if this is nessecary or may also be driven internally by the Aclk source. Please also somebody check on that.


I am also currently experiencing problem for uploading
i hope they fix it soon.    

[Olaf.Mandel]

[...]
Layer 2 for gnd is because it gives the least inductance for the GND via's.
Same reason for using layer 3 for VCCINT.
Layer choices isn't that critical, but having proper power planes, especially for Gnd IS important.
Sure lots of times the most crazy routing works, but it's best to do what you can to not end up
with a board that behaves in "mysterious ways" 

Could you please give me a link so I can  have a look at the pcb file?

How does layer GND=layer 2 and VCCINT=layer 15 (so vias for both signals) compare to GND=layer 1 and VCCINT=layer 16 (so only vias in one signal)? If you want to minimize inductance, then this should be even better. And having GND on layer 1 means that there is no ground below every pad, so less capacitance as well. Or does one want to have lots of that?

It should now be much easier to change GND to layer 2, since VCCAUX is gone. But then we have MANY more vias! Current via count is 261 vias, price break is at 300.

[fizzisist]

I uploaded a new version of the schematic, board and PDF+PNG to github. Couldn't upload to dropbox for some weird reason (upgrade to newest Flash?, worked yesterday).

Changes:

• VCCINT is now split into two signals VCCINT0 and VCCINT1 for the two different FPGAs
• VCCAUX is gone, merged with VCCIO
• Layer 2 contains no polygon anymore
• The different FPGAs are spaced further apart, polygons no longer touching
• The termination resistors are folded to the back, reducing the size by half

TODO:

• Unfold the bus to not have several signals on top of each other
• Merge with PSU (again) and MCU

I did this before pusle posted his more detailed explanation. Can you actually look at the file from github and say how bad you think this is?

Also: can someone copy the files to dropbox, because I cannot.

I uploaded your files to Dropbox (I don't use the web interface). I don't have Eagle on this computer, so I wasn't able to look closely at your changes.

To your other question about layer stackup, part of the reason to put GND and VCCINT on inner layers close to eachother is that it increases the capacitance between the two, thus helping with decoupling. Having them as complete planes helps reduce the size of current loops, because the return path for a signal (for example) will always run directly below the trace on the outer layer above it. At least that's my understanding.

[newMeat1]

To your other question about layer stackup, part of the reason to put GND and VCCINT on inner layers close to eachother is that it increases the capacitance between the two, thus helping with decoupling. Having them as complete planes helps reduce the size of current loops, because the return path for a signal (for example) will always run directly below the trace on the outer layer above it. At least that's my understanding.

Sounds like somebody read the document I sent   

[li_gangyi]

Personally it doesn't look too bad to me, I just need to check that we are meeting requirements for decoupling capacitors.

GND on layer 2 would be best, however we'd have to put in blind vias to link up the top to 2nd in order to still make the rest of the space usable. I might have gone overboard when testing it out though, I had vias going from almost every node to the 2nd layer.

I'll add in the PSUs to the new board layout later.

Edit: Ok added it in, we're gonna have to touchup the IO routing abit, let me finish up the rest in the next few hrs.