Modular FPGA Miner Hardware Design Development

[fizzisist]

li_gangyi, I looked at your PSU schematic in the Dropbox folder. I hope you don't mind, but I made some changes, mostly cosmetic. I think what you have looks good. Some details on the component packages and values can be discussed later (usually depends mostly on availability and price).

In addition we should further investigate on the matter wich changes to our currently desired setup are nessesary to allow the use of different programms than for bitcoin.

I think this is going to be a difficult requirement to achieve. If we can think of some minor changes that make the design more flexible, great, but I have my doubts. Remember, we are building this because the generic and flexible evaluation boards out there are too expensive. The point was to take out all the other stuff and build a board with none of the unnecessary features that those other boards have, and therefore reduce the price.

Please don't let my doubts completely dissuade you from trying, though.

[li_gangyi]

li_gangyi, I looked at your PSU schematic in the Dropbox folder. I hope you don't mind, but I made some changes, mostly cosmetic. I think what you have looks good. Some details on the component packages and values can be discussed later (usually depends mostly on availability and price).

In addition we should further investigate on the matter wich changes to our currently desired setup are nessesary to allow the use of different programms than for bitcoin.

I think this is going to be a difficult requirement to achieve. If we can think of some minor changes that make the design more flexible, great, but I have my doubts. Remember, we are building this because the generic and flexible evaluation boards out there are too expensive. The point was to take out all the other stuff and build a board with none of the unnecessary features that those other boards have, and therefore reduce the price.

Please don't let my doubts completely dissuade you from trying, though.

I've looked at component availability, digikey should have all the parts I've put down, capacitor ESRs are pretty critical.

I'm also doubting that this board will be useful as an experimental platform, alot of the GTP is not present, there's no memory at this point in time, even the PSU for Vccio is shared with Vccaux, which is non optimal if there's alot of IO activity. We're gonna also have to add some connectors for the IOs (more routing, layers probably)

We could work out all of these limitations, but in the end I think our board will just end up being more expensive. I wouldn't go for it.

[O_Shovah]

K so we will have a pure miner in the first run. No risk no fun

[li_gangyi]

We can always minimise risks, populate the PSU first before the FPGA, populate only 1 FPGA at the start, and if all else fails, remove and reball the FPGAs and list em on ebay I guess...

How are we planning to power the MSP430? 2.5v? And does bitcoin mining require any sort of external memory buffer? I'm not familiar with FPGAs enough. We also need to think about the clock source.

Maybe some1 can draw up a block diagram of what the final result will look like and then we can solve each one step by step.

[sirky]

I have no technical expertise, so I cannot really comment on the discussion, but I just want to let you guys know that I think this project is really cool. I would probably be willing to buy one just to play around with it as long as the total cost to get everything up and running is <= a grand!

[fizzisist]

How are we planning to power the MSP430? 2.5v? And does bitcoin mining require any sort of external memory buffer? I'm not familiar with FPGAs enough. We also need to think about the clock source.

Maybe some1 can draw up a block diagram of what the final result will look like and then we can solve each one step by step.

Yes, the MSP430 will use the 2.5V rail. It should put an insignificant load on that line, on the order of 5 mA. I agree that a block diagram is in order. I think we also could use a document describing what kind of functions the MCU will be responsible for. Both of these could be placed in the Dropbox. I'll try to work on the block diagram if I have time today.

I have no technical expertise, so I cannot really comment on the discussion, but I just want to let you guys know that I think this project is really cool. I would probably be willing to buy one just to play around with it as long as the total cost to get everything up and running is <= a grand!

Good to know that there is more interest! If we can pool our money together for the first production run, we can order more boards, and therefore lower the price per board significantly. This is something we will need to start discussing after the first prototypes are finished.

[O_Shovah]

I have no technical expertise, so I cannot really comment on the discussion, but I just want to let you guys know that I think this project is really cool. I would probably be willing to buy one just to play around with it as long as the total cost to get everything up and running is <= a grand!

Allways feels good to read such comments.Thanks
Any precise price estimations would be fortune telling right now but i asume you will get more than one board of you 1000$.

Yes, the MSP430 will use the 2.5V rail. It should put an insignificant load on that line, on the order of 5 mA. I agree that a block diagram is in order. I think we also could use a document describing what kind of functions the MCU will be responsible for. Both of these could be placed in the Dropbox. I'll try to work on the block diagram if I have time today.

That would be great.
I am certainly becoming more moderator than constructor, as we are moving further into detail.So i will mostly do the organisation.
I just can't keep my learning at the speed we are advancing, so i hope you bear with me even if i don't understand all technical details.(But as a student i'm allways happy to learn )    

[fizzisist]

I created a first try at a very high level block diagram. Mainly, my idea was to have a "straw man" that we can all have in mind when we discuss. Hopefully, it will get better as the ideas get more refined.

This is uploaded to the dropbox at Documentation/Block_Diagram, in PPT format. Here's a link to a PNG of the diagram, so that those without access can see it, too:

http://dl.dropbox.com/u/13472215/block_diagram_daughter.png

Please point out any mistakes I made or edit the file yourself.

[Olaf.Mandel]

[...]
I'm also doubting that this board will be useful as an experimental platform, alot of the GTP is not present, there's no memory at this point in time, even the PSU for Vccio is shared with Vccaux, which is non optimal if there's alot of IO activity.[...]

Actually, could you not share those? The VCCaux supply powers the frequency synthesizers in the FPGA and needs to be filtered to a better degree than VCC_O. This is apparently normally done by taking a supply to generate VCC_O and then adding an LC-filter to get VCCaux.

[li_gangyi]

Actually, could you not share those? The VCCaux supply powers the frequency synthesizers in the FPGA and needs to be filtered to a better degree than VCC_O. This is apparently normally done by taking a supply to generate VCC_O and then adding an LC-filter to get VCCaux.

I've looked at the spec sheet for Vccaux specifications, only real limitation is I do not allow more then 5% ripple to be exceeded on the design. At the current number of IOs that we need (non of our IOs need to be driven very hard, or very fast), that's not going to be a problem. As long as we include the suggested number and layout for decoupling caps it's going to be sufficient.

I've looked at the Xilinx forums regarding this matter, and nothing seems to suggest otherwise.

http://forums.xilinx.com/t5/Spartan-Family-FPGAs/Doubt-regarding-VCCAUX-voltage-level-and-its-separate-power/td-p/162346

[O_Shovah]

I just made a little Block Diagramm for the motherboard and stored it in the Box.

[Olaf.Mandel]

Uploaded new FPGA section of board to dropbox.



Changes compared to last time:

• Changed all unused pins to GND, pull HSWAPEN high for floating pins during configuration
• Use 4 layers
• Added *.dru file for pcbcart service
• Assign one layer each for the different signals:
  
  • 1: GND
  • 2: VCCIO
  • 15: VCCAUX
  • 16: VCCINT
• Placed smallest caps on the backside
• Compactified the board: 83x28mm²

Still to do:

• Get rid of separate VCCAUX and VCCIO as suggested by li_gangyi?
• Are the buses ok like that (all wires on top of each other)?
• Check everything.
• Write a summary of the *.dru.
• Further compactify the resistors (are all needed?) and largest caps..

[Olaf.Mandel]

Just replaced the *.png and *.brd file: there were some unrouted signals left... If you already got the old version: get the new one.

[O_Shovah]

I have just created and uploaded a further Block Diagramm that shows my idea of how work parts mostly autonom could be devided to serveral workgroups if desired.

As there would be:

- Power supply ( design, testing,optimisation,supply for the motherboard) i consider this a job for li_gangyi as he has already started on this and seems to have the nessecary equipment.

- Motherboard (Design, layout) fairly open to anyone maybe best for those not so firm on layouts in Eagle ( like me )

- Bus System and MSP430 ( Design, Code programming)  i my eyes best fit for,  bahnfire, mamok and all of you with experience in programming an BUS systems

- FPGA I/O ( Design, prerouting) maybe for Olaf.Mandel and others interested in the FPGA

And after that step we start putting these single blocks together and in the end finalise a protoype PCB.
The names i gave a just suggestion originated from my impression who has wich expertise. Of course everyboda is free to choose the subject he or she likes.

Please give your comment.


So in the end again.  We are still just 4 people in the Dropbox .  So i ask everybody else interested in the Files to notify me their email adress so i may add them.

[li_gangyi]

I've looked at the new layout, it looks alot better then the previous one we had. I wouldn't stack the signals like that, the PCB material in between effectively becomes a capacitor and can cause all kinds of weird things to happen. I think we should route it as per normal on 1-2 layers.

I'm thinking of splitting the FPGAs in the middle, and then adding the MCU and VccAUX PSU in there, and the VccINT supplies individually above each FPGA. It'll simplify the routing for the output of the PSU (we still will have challenges related to the 12V in bus, but I think that's solvable) and create a lower ohmic drop since current doesn't have to travel from left to right.

[O_Shovah]

I'm thinking of splitting the FPGAs in the middle, and then adding the MCU and VccAUX PSU in there, and the VccINT supplies individually above each FPGA. It'll simplify the routing for the output of the PSU (we still will have challenges related to the 12V in bus, but I think that's solvable) and create a lower ohmic drop since current doesn't have to travel from left to right.

Considering the high current on the Vint rail. Wich cooper thikness would you advise to keep losses and heating low ? 70um or more ?

[li_gangyi]

Since we have dedicated layers for power, I don't think thickness is an issue at 10A, we'd just need a wider trace. 35um is cool, VccINT is also on the backside, exposed to free air (instead of say in the middle), that really helps out alot on heat.

[O_Shovah]

Ok so as i proposed before. May you do the first standalone version of the power supply ?

You said you had the necessary testing equipment so the performance and stability tests would certainly fit for you.

[Olaf.Mandel]

Since we have dedicated layers for power, I don't think thickness is an issue at 10A, we'd just need a wider trace. 35um is cool,

Really? The current still needs to go to the top layer and the pads. There the trace width is 0.3mm only! Admittedly, the traces are short (for VCCint at least). But wouldn't you want a bit more copper for these traces? And for GND, I had no choice but to use rather long traces around the centre of the FPGA.

VccINT is also on the backside, exposed to free air (instead of say in the middle), that really helps out alot on heat.

I mostly did that because for some manufacturers (not pcbcart, apparently) the outer layers can be thicker than the inner layers.

[Olaf.Mandel]

I hate to draw the attention away from technical the discussion, but I think we are heaping up a lot of future legal hassle at the moment:

IANAL, but as far as I know all creative work is automatically copyrighted to the creator. Publishing it (even on something like dropbox) doesn't change that at all. So if we continue like we currently do, in the end we have a design that may contain key components we don't have permission to use! The FOSS community has a lot of experience with this sort of cr*p, so why don't we take a page from them? Our options at the moment are:

• We put everything into the public domain. Everyone with write access to the dropbox folder has to agree to that and it needs to be stated in a prominently visible file on dropbox.
• We transfer copyright to a single entity (say: O_Shovah's real identity). Again: everyone with write access has to agree. Then O_Shovah has to set a license under which we all can use his copyrighted work, preferably stated in a prominently visible file. He can change his mind, later.
• We each explicitly assign copyright to our work (an AUTHORS file seems to work) and we all agree on a license that applies to the work (LICENSE file).

My own feeling is that this is too cool to just "throw away" by putting it into the public domain. On the other hand, no offence O_Shovah, but I would not want to assign copyright to you. My personal preference is to use a GPL license: there are some issues with applying that to hardware designs, but they seem to be minor. And it works perfectly for the software and firmware.

I am not saying that I will stop working on the project if one of the first options is chosen or if it is a different license. But I think we need to agree on this quickly, before even more people and more copyright holders enter here.