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Question: Wich FPGA shall be used on our prototype ?
Xilinx Spartan 6 LX 150 - 17 (70.8%)
Altera Cyclone IV 75k - 7 (29.2%)
Total Voters: 24

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Author Topic: Modular FPGA Miner Hardware Design Development  (Read 112088 times)
Entropia
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September 21, 2011, 07:04:12 AM
 #641

Well, I have to say that I have had my own FPGA cluster under development for some time. I originally designed it for hash breaking (such as MD5) but why not Bitcoin mining as well. The specification is quite a bit different than what has been proposed here. My design has one baseboard with an Atmel AVR USB-enabled microcontroller that handles all host communication and FPGAs communicate via I2C. The baseboard provides a JTAG chain and a 5V/5A power supply. If some slack conditions are met (i.e. I2C and JTAG voltage levels) then the system is completely agnostic to what is doing the actual processing. The mechanical layout is copied from Arduino, so that modules simply stack on top of each other.

Currently I am in the process of laying out the baseboard and after that I will probably do a simple Spartan-3E QFP processing unit. Sure, S3E sucks at mining BTC hashes but it's a start and you can later on develop more sophisticated units like S6LX150.

Summa summarum: I am hesitant to help with design that I disagree with (the design discussed in this thread). That and I know absolutely nothing about the TI MSP430. But I'll keep watching this space...
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ngzhang
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September 23, 2011, 06:22:02 PM
 #642

Hi guys. What's up with this development? Nothing has happened in a few weeks, is it dead?

ngzhang: Your miner board is very interesting! Do you have any real-world performance data? Is the board stable? What's the current consumption on the FPGAs? I'm looking forward to the schematics and other files on that board. Smiley

These days, I fixed some bugs on the hardware and relayout the PCB. Another 10 boards are under manufacturing. Coming out soon.
On the firmware side:
With a single FPGA running LX150_makomk_Test's code, a speed of 120MH/s perFPGA has been reached. looks very stable. We only use a -2 device.
with ourselves' UART communication mining code, a test version could mining @ 50MH/s and not very stable, maybe there are some P&R problems. Because lack of time, we just checked the function, it works.
Now we are testing the the FPGA mining chain, this part is still under coding.
The mining core is the most important part of this project, so  after finish the mining chain architecture, we will put 100% efforts on this core.
Correct makomk's core use SLR16s to save resources, but this cause a terrible P&R difficulty. But if don't use the SLR_16s, there are not enough registers. Solve this conflict will lead a single FPGA to 250MH/s at least.

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September 26, 2011, 05:43:12 PM
 #643

IMO the upper limit for 6s150 -3 is around 200MH/s w/o overclocking.
ArtForz was claiming ~193MH/s with his design; closest I've gotten is ~156MH/s.
And getting that to build through ISE was quite a challenge.

If you can reach 250M/s in -2, you are probably one of the top 10 FPGA designers in the world
and should be working for the finance sector or govt/military instead of wasting time on bitcoin.  Grin

-rph

Ultra-Low-Cost DIY FPGA Miner: https://bitcointalk.org/index.php?topic=44891
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September 26, 2011, 07:31:05 PM
 #644

IMO the upper limit for 6s150 -3 is around 200MH/s w/o overclocking.
ArtForz was claiming ~193MH/s with his design; closest I've gotten is ~156MH/s.
And getting that to build through ISE was quite a challenge.

If you can reach 250M/s in -2, you are probably one of the top 10 FPGA designers in the world
and should be working for the finance sector or govt/military instead of wasting time on bitcoin.  Grin

-rph


yeah, I think so. Grin

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sadpandatech
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November 14, 2011, 03:52:49 PM
 #645

  Has anyone tested the -3 grade at 1.27v or above for error rate, etc?

If you're not excited by the idea of being an early adopter 'now', then you should come back in three or four years and either tell us "Told you it'd never work!" or join what should, by then, be a much more stable and easier-to-use system. - GA
It is being worked on by smart people. -DamienBlack
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November 14, 2011, 06:30:37 PM
 #646

No i haven't tested it at that core voltage yet.
I asume this would also considerably shorten the life span.

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November 14, 2011, 08:21:38 PM
 #647

No i haven't tested it at that core voltage yet.
I asume this would also considerably shorten the life span.

  But, by how much? Assuming proper cooling, the rated max for VccInt is 1.32. Above 1.25 may not leave enough room for spikes on power down, but shouldn't raise operational temp all that much.  If I ever get any of the things here I will test some out on extended runs.

If you're not excited by the idea of being an early adopter 'now', then you should come back in three or four years and either tell us "Told you it'd never work!" or join what should, by then, be a much more stable and easier-to-use system. - GA
It is being worked on by smart people. -DamienBlack
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November 15, 2011, 05:48:33 PM
 #648

I might try on one of my solder/Power supply/stability testboards since it seems i wont need them for now.
I will runn some Tests an report in case i cook them Wink
If the competing approaches reall reach markt as promised this development might be obsolete since this developing thread seems down to me alone.
I cant keep the pace. 

So we will see.

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November 15, 2011, 07:27:58 PM
 #649

I like this idea. Is the project still alive?

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November 15, 2011, 07:36:41 PM
 #650

As i stated above i personnaly keep pursuing this idea since i started the thread.
But it seems im the only one working on this right now beside my job so its extremly slow.

If anyone wishes to help push this concept on, she or he is very welcome. 

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