KNCMiner and their 'magic' SHA256 alogorithm

[J35st3r]

And speaking of said, here are some questions you shouldask anyone wanting your money up front for any asic product:

1. Who is the silicon foundry?
2. Are you using a Multi Project Wafer service or a full mask set?
3. What is the chip size?
4. How many pipelines does it have and what is the operating frequency?
5. What is the target package type?
6. If you are using a full mask set ($1.6 - $2.3 Million for 28nm) who or how are you financing it and what are your contingency plans if you need a respin?
7. To get '90 day' production you need a lot of chips, meaning you need several wafers (costing 15 - 30k dollars each in a small geometry). Refer to 6 above.
8. What software tools have you used for development and if they are commercial ones like Cadence, exactly how have you financed them up to now?
9. What happens to my money/order if you miss the 90 day target?
10. Will you publish an order backlog summary for purchasers to examine?
11. Will you publish the invoice for NRE for purchasers to see? (ie to see that it really is x nm)

Feel free to add your own. There is absolutely no reason for any company wanting your money NOT to answer these questions.

There has been 2 open days at KNCminer. They answered pretty much all the questions asked to them. You could have sendt your questions with someone attending.

Wow, the fanboi's have certainly been to town on this one. I'm going to side with brontosaurus as his questions 1 thru 8 are very pertinent.

As for the open day, from BitcoinOrama's report https://bitcointalk.org/index.php?topic=232852.0 the most telling fact that was disclosed was that KNCMiner's ASIC has a huge die size and they have absolutely no wafer or packaged device test strategy. They are just going to solder the chips on boards and hope for the best. There will be tears  

[blastbob]

Tears of joy

[VeeMiner]

And speaking of said, here are some questions you shouldask anyone wanting your money up front for any asic product:

1. Who is the silicon foundry?
2. Are you using a Multi Project Wafer service or a full mask set?
3. What is the chip size?
4. How many pipelines does it have and what is the operating frequency?
5. What is the target package type?
6. If you are using a full mask set ($1.6 - $2.3 Million for 28nm) who or how are you financing it and what are your contingency plans if you need a respin?
7. To get '90 day' production you need a lot of chips, meaning you need several wafers (costing 15 - 30k dollars each in a small geometry). Refer to 6 above.
8. What software tools have you used for development and if they are commercial ones like Cadence, exactly how have you financed them up to now?
9. What happens to my money/order if you miss the 90 day target?
10. Will you publish an order backlog summary for purchasers to examine?
11. Will you publish the invoice for NRE for purchasers to see? (ie to see that it really is x nm)

Feel free to add your own. There is absolutely no reason for any company wanting your money NOT to answer these questions.

There has been 2 open days at KNCminer. They answered pretty much all the questions asked to them. You could have sendt your questions with someone attending.

Wow, the fanboi's have certainly been to town on this one. I'm going to side with brontosaurus as his questions 1 thru 8 are very pertinent.

As for the open day, from BitcoinOrama's report https://bitcointalk.org/index.php?topic=232852.0 the most telling fact that was disclosed was that KNCMiner's ASIC has a huge die size and they have absolutely no wafer or packaged device test strategy. They are just going to solder the chips on boards and hope for the best. There will be tears  

I concur, these are all really good questions

[notme]

It's called trying to inflate the actual performance of your product and/or design knowledge. If your product is good, quote firm numbers based on hard, verifiable FACTS rather than allude to 'improvements' to a mathematical process which has data dependencies which cannot be changed or improved.

The academics who wrote the paper quoted are experts in their field - Dadda has an adder type named after him - and designed a method of reducing delay paths on an actual asic. They did'nt change or say they could change an algorithm. KNC claim to have an 'improved' algorithm, and that is just plain rubbish. Ask any mathematician.

Any respectable company would not make such ridiculous claims, if KNC have indeed used the methods from this paper in their design,then they should acknowledge it. Hence my annoyance.

Incidentally, Dadda and co. got their SHA256 engine to run at 'a clock speed of well over 1Ghz' on a 130nm process.

I'm a mathematician and I think you are splitting hairs.  It may not be acceptable in a mathematical journal, but in common usage it is acceptable to me to label an improved algorithm implementation as simply an improved algorithm.  Most people don't know the difference and it conveys the idea that they have some special sauce that makes theirs better than a naive implementation.

[idee2013]

It's called trying to inflate the actual performance of your product and/or design knowledge. If your product is good, quote firm numbers based on hard, verifiable FACTS rather than allude to 'improvements' to a mathematical process which has data dependencies which cannot be changed or improved.

The academics who wrote the paper quoted are experts in their field - Dadda has an adder type named after him - and designed a method of reducing delay paths on an actual asic. They did'nt change or say they could change an algorithm. KNC claim to have an 'improved' algorithm, and that is just plain rubbish. Ask any mathematician.

Any respectable company would not make such ridiculous claims, if KNC have indeed used the methods from this paper in their design,then they should acknowledge it. Hence my annoyance.

Incidentally, Dadda and co. got their SHA256 engine to run at 'a clock speed of well over 1Ghz' on a 130nm process.

I'm a mathematician and I think you are splitting hairs.  It may not be acceptable in a mathematical journal, but in common usage it is acceptable to me to label an improved algorithm implementation as simply an improved algorithm.  Most people don't know the difference and it conveys the idea that they have some special sauce that makes theirs better than a naive implementation.

+1

this is what i already said...

[KS]

It's called trying to inflate the actual performance of your product and/or design knowledge. If your product is good, quote firm numbers based on hard, verifiable FACTS rather than allude to 'improvements' to a mathematical process which has data dependencies which cannot be changed or improved.

The academics who wrote the paper quoted are experts in their field - Dadda has an adder type named after him - and designed a method of reducing delay paths on an actual asic. They did'nt change or say they could change an algorithm. KNC claim to have an 'improved' algorithm, and that is just plain rubbish. Ask any mathematician.

Any respectable company would not make such ridiculous claims, if KNC have indeed used the methods from this paper in their design,then they should acknowledge it. Hence my annoyance.

Incidentally, Dadda and co. got their SHA256 engine to run at 'a clock speed of well over 1Ghz' on a 130nm process.

I'm a mathematician and I think you are splitting hairs.  It may not be acceptable in a mathematical journal, but in common usage it is acceptable to me to label an improved algorithm implementation as simply an improved algorithm.  Most people don't know the difference and it conveys the idea that they have some special sauce that makes theirs better than a naive implementation.

Nope, not right. It's not because ppl are ignorant of the jargon that you have to lie to them. If you don't even have the integrity to NOT lie to ppl who don't know what you are talking about...

[Bitcoinorama]

http://youtu.be/g_59IoosY2g

[idee2013]

TL;DR version of this thread.

Spew FUD around,

Don't read KnC Main Topic or Bitcoinorama's Open day questions,

Ask questions knowing full well they could have been asked at the open day,

refuse to have questions answered by logic or reason,

ask everyone to go do research for you,

still say scam/voodoo after evidence suggests otherwise,

Proceed to spew more FUD.

+1+1+1

[titomane]

Whoever does not believe in KNC do not buy. There are almost the only ones that sell asics. I understand that people wary of all manufacturers. Because until now only been hoaxes. Avalon except batch 1 and 2.
But there have been more than 2 days to ask them and expose them.

[KS]

Huey, Dewey and Louie

[notme]

It's called trying to inflate the actual performance of your product and/or design knowledge. If your product is good, quote firm numbers based on hard, verifiable FACTS rather than allude to 'improvements' to a mathematical process which has data dependencies which cannot be changed or improved.

The academics who wrote the paper quoted are experts in their field - Dadda has an adder type named after him - and designed a method of reducing delay paths on an actual asic. They did'nt change or say they could change an algorithm. KNC claim to have an 'improved' algorithm, and that is just plain rubbish. Ask any mathematician.

Any respectable company would not make such ridiculous claims, if KNC have indeed used the methods from this paper in their design,then they should acknowledge it. Hence my annoyance.

Incidentally, Dadda and co. got their SHA256 engine to run at 'a clock speed of well over 1Ghz' on a 130nm process.

I'm a mathematician and I think you are splitting hairs.  It may not be acceptable in a mathematical journal, but in common usage it is acceptable to me to label an improved algorithm implementation as simply an improved algorithm.  Most people don't know the difference and it conveys the idea that they have some special sauce that makes theirs better than a naive implementation.

Nope, not right. It's not because ppl are ignorant of the jargon that you have to lie to them. If you don't even have the integrity to NOT lie to ppl who don't know what you are talking about...

Get a life.  There are much bigger things to worry about than a marketing department reducing a phrase from 3 long words to 2 long words that convey the same exact meaning to 90% of the population.

[Xian01]

float Q_rsqrt( float number )
{
  long i;
  float x2, y;
  const float threehalfs = 1.5F;

  x2 = number * 0.5F;
  y  = number;
  i  = * ( long * ) &y;
  i  = 0x5f3759df - ( i >> 1 );
  y  = * ( float * ) &i;
  y  = y * ( threehalfs - ( x2 * y * y ) );

  return y;
}

... is the only magic I recognize.

[notme]

float Q_rsqrt( float number )
{
  long i;
  float x2, y;
  const float threehalfs = 1.5F;

  x2 = number * 0.5F;
  y  = number;
  i  = * ( long * ) &y;
  i  = 0x5f3759df - ( i >> 1 );
  y  = * ( float * ) &i;
  y  = y * ( threehalfs - ( x2 * y * y ) );

  return y;
}

... is the only magic I recognize.

Hooray for exploiting floating point notation!

[Loredo]

It's called trying to inflate the actual performance of your product and/or design knowledge. If your product is good, quote firm numbers based on hard, verifiable FACTS rather than allude to 'improvements' to a mathematical process which has data dependencies which cannot be changed or improved.

The academics who wrote the paper quoted are experts in their field - Dadda has an adder type named after him - and designed a method of reducing delay paths on an actual asic. They did'nt change or say they could change an algorithm. KNC claim to have an 'improved' algorithm, and that is just plain rubbish. Ask any mathematician.

Any respectable company would not make such ridiculous claims, if KNC have indeed used the methods from this paper in their design,then they should acknowledge it. Hence my annoyance.

Incidentally, Dadda and co. got their SHA256 engine to run at 'a clock speed of well over 1Ghz' on a 130nm process.

I'm a mathematician and I think you are splitting hairs.  It may not be acceptable in a mathematical journal, but in common usage it is acceptable to me to label an improved algorithm implementation as simply an improved algorithm.  Most people don't know the difference and it conveys the idea that they have some special sauce that makes theirs better than a naive implementation.

Nope, not right. It's not because ppl are ignorant of the jargon that you have to lie to them. If you don't even have the integrity to NOT lie to ppl who don't know what you are talking about...

Get a life.  There are much bigger things to worry about than a marketing department reducing a phrase from 3 long words to 2 long words that convey the same exact meaning to 90% of the population.

I think we've discovered here why marketing guys use words that end in -ize (-ise for our friends in the UK).  If they said:  

"Our wizards use tricks only cool kids know to optimize the run time of the SHA-256 algorithm",

can any of the attendant word smiths take issue with it?

EDIT: Wait, I'm answering my own question.  "Optimum" is a superlative; there is only one.  To assert something is optimized implies there is no better way to achieve a particular objective.  Since that is difficult to establish unambiguously, anyone who would state such is certainly a charlatan.

Tomorrow, on Dancing with the Angels on the Head of the Pin, we'll be discussing the near-criminal practice of claims that various compliers perform "optimization."

[brontosaurus]

Well, well. Seems my post has caused a little bit of debate and controversy.

In answer to some of what I assume are the adolescents among us, I did read the visit 'report' to KNC and I can only surmise it was written by someone who is a True Believer, much like those misguided souls who believe in UFO's and related claptrap. From the little factual content presented, there emerge further disturbing facts:

1. Anyone with the slightest knowledge of the asic industry would tell you that silicon foundries are not
    at all excited at the prospect of possibly a few hundred k asics for 28nm. To suggest they will
    'compete' to get KNC's business is a very quaint idea, but totally untrue. KNC will have to convince
    a foundry to give them access to the technology, and it's not a dead cert that they will. I know for a
    fact that foundries have been 'plagued' (their words, not mine) by people calling them up with plans
 for
    Bitcoin asics,who don't seem to have the first idea what is actually involved.

2. Designing an FPGA is totally different from designing an asic. I'm not going to go into the details, just
    ask anyone who works in the industry. To think that you just take the same HDL code and out pops
    your asic is not the case. Any competent engineering graduate could write the HDL for a SHA256
    engine in an afternoon, and put together a compiled FPGA solution in a few days, at most.

    To do the same in an asic is a totally different ball game. Clearly the lads at KNC either have never
    done this,or are making some potentially fatal assumptions.

[Syke]

    To do the same in an asic is a totally different ball game. Clearly the lads at KNC either have never
    done this,or are making some potentially fatal assumptions.

Sounds like the best they've done before is a 40nm hardcopy.

Marcus: We have done designs that are much more complex...

Me: What Was that?

Marcus: That was a hardcopy. 40Nm hardcopy.

[brontosaurus]

Shit, hit the wrong key.

To continue on my response;

3. I could not believe my eyes when I read that the plan is to simply solder the prototype chips straight
    onto the board without testing. This is an unbelievably stupid plan; any engineer worth their salt
    would be horrified. In asic design there is a well worn path for carrying out evaluation of new chips,
    and this isn't it. It's amateurish and totally unworkable. Plus, it suggests that they have no actual
    test strategy or production test program. But hey, who needs it? (Intel, AMD ............)

    But if you trust your thousands of dollars to these guys, good luck to you.

As regards some of the other comments about semantics, my initial post was about the fact that KNC were misleading potential customers by claiming they had something which they don't. It's dishonest, no
matter what spin you try to put on it. I've still not seen one solid piece of data from them or any of their
'fans' about their design architecture, die size or contingency plans if things go wrong, and if was giving
my money to them, these are not 'optional' facts.

What I did initially see was the specification of their Mars miner which seemed to be able to sold for less than a third of the price that the FPGAs alone within it cost. Bad marketing? Poor engineering? Voodoo?
Who knows, but if you want to be successful in building a complex device costing many hundreds of thousands of dollars in tooling costs, you'd better get your paperwork and specifications right.

The thought of these guys with millions of dollars of pre order money horrifies me - until I get some
straight answers at least.

But again, if you want to be a 'Believer', who am I to tell you otherwise? I've spent my entire
professional life dealing in facts, specifications and good solid engineering methodology. My 'belief'
in this system has always worked, and will continue to do so.

But greed blinds most people. Just look at what's happened to the financial fantasies of the BFL pre
order herd.

[k9quaint]

2. Designing an FPGA is totally different from designing an asic. I'm not going to go into the details, just
    ask anyone who works in the industry. To think that you just take the same HDL code and out pops
    your asic is not the case. Any competent engineering graduate could write the HDL for a SHA256
    engine in an afternoon, and put together a compiled FPGA solution in a few days, at most.

    To do the same in an asic is a totally different ball game. Clearly the lads at KNC either have never
    done this,or are making some potentially fatal assumptions.

Or they wanted to build the boards, case, cooling solutions and integrate all of it (and test it) in parallel while OrSoc builds the ASIC (which is probably pin-out compatible with the FPGA). Yes, laying out an ASIC is different than laying out an FPGA and that is probably why they went with a serious ASIC design house instead of trying to do it themselves. However, there are quite a few "tricks" to be done while setting up a 128 stage pipeline be it on ASIC or on FPGA.

[titomane]

Shit, hit the wrong key.

To continue on my response;

3. I could not believe my eyes when I read that the plan is to simply solder the prototype chips straight
    onto the board without testing. This is an unbelievably stupid plan; any engineer worth their salt
    would be horrified. In asic design there is a well worn path for carrying out evaluation of new chips,
    and this isn't it. It's amateurish and totally unworkable. Plus, it suggests that they have no actual
    test strategy or production test program. But hey, who needs it? (Intel, AMD ............)

    But if you trust your thousands of dollars to these guys, good luck to you.

As regards some of the other comments about semantics, my initial post was about the fact that KNC were misleading potential customers by claiming they had something which they don't. It's dishonest, no
matter what spin you try to put on it. I've still not seen one solid piece of data from them or any of their
'fans' about their design architecture, die size or contingency plans if things go wrong, and if was giving
my money to them, these are not 'optional' facts.

What I did initially see was the specification of their Mars miner which seemed to be able to sold for less than a third of the price that the FPGAs alone within it cost. Bad marketing? Poor engineering? Voodoo?
Who knows, but if you want to be successful in building a complex device costing many hundreds of thousands of dollars in tooling costs, you'd better get your paperwork and specifications right.

The thought of these guys with millions of dollars of pre order money horrifies me - until I get some
straight answers at least.

But again, if you want to be a 'Believer', who am I to tell you otherwise? I've spent my entire
professional life dealing in facts, specifications and good solid engineering methodology. My 'belief'
in this system has always worked, and will continue to do so.

But greed blinds most people. Just look at what's happened to the financial fantasies of the BFL pre
order herd.

With all due respect
I do not understand, why not make a business / device? This wasting time, if you've always had good results on your projects with your methodology.

[brontosaurus]

With all due respect, there is no place in my profession for deception, exaggeration, poor design, dubious methodology and 'try it and hope for the best' attitude.