KNCMiner and their 'magic' SHA256 alogorithm

[keyzersoze]

The way i understand it, the raise from 250 to 350 wasnt related to the 30% "algorithm" speed increase.
It might have been just an increase in the ammount of chips they were planning to put in every miner, or just new, revised estimates of what speeds the chips will actually work at.

[1715055203]

1715055203

[1715055203]

1715055203

[1715055203]

1715055203

[1715055203]

1715055203

[1715055203]

1715055203

[keyzersoze]

"This device is being designed in parallel by the ORSoC engineers and will offer industry leading performance and power consumption per GH.The final specifications for this device are being ironed out now but we can confirm the following.Minimum 175/350GH/s per device.28nm Standard ASICAn additional gain of 30% more hashing when the advanced algorithms provided by ORSoC are applied"

Those are the specs for the product that i bought, as advertized by KNC, and have gotten it verbally confirmed twice by both Sam and Marcus.
So that will be what i expect, and hold KNC to, come delivery time.

[k9quaint]

But it's all too easy to get carried away with lots of pre-order cash and think you're some kind of Bitcoin or Silicon god.

Not really, real engineers are not driven by sales figures.

Technical history of asic designs suggests that such arrogance usually gets rewarded with humiliating failure, and your boys in KNC  / Orsoc are just about to go down the same sorry path.

Actually, its quite the opposite. Modern ASIC design tools employed by competent engineers usually produce working products. It is only in areas where you are pushing the boundaries of what can be done like GPUs and CPUs that is fraught with failure. SHA256 is not pushing any design boundaries. They are using a well established geometry at 28nm. It should be a layup. BFL pretended to have expertise in ASICs and you should not judge actual engineering firms (OrSoc) by BFL's track record.

I mean, no chip testing methodology - just solder them to a board and see if they work?

Please prove that OrSoc & KNCMiner have no chip testing methodology. Links to posts where they say they are "employing no chip testing" would be sufficient.

It's really a pity they won't put aside the pseudoscience and speculation and actually publish a proper datasheet for the product, just like any regular chip supplier.

The product does not yet exist. They are being careful about setting expectations. They don't want to "BFL" their customers.

Something that tells their purchasers exactly what they are promising and - under European Law - they must then deliver (to buyers in the EU at least). It would certainly close off this thread if they did so, and might silence the skeptics, including me.

I am sure after the product exists, they will document what it can do. Right now they are releasing estimates.
You confuse absence of evidence with evidence of absence and post no evidence of your wild conjecture.
Please provide citations for your statements in the future.

It's kind of obvious from the above that the writer has never actually worked in any commercial company, or, possibly in any company at all.

Draw your own conclusions.

Wrong again.
All you have denials, innuendo, and scare tactics. You haven't linked to a single piece of evidence to support your wild claims. You created the brontosaurus account to post crazy sauce in this thread.

That fact that you exist is actually good evidence that KNC is not a scam. Otherwise, why would shills like you both spreading FUD about them?

[Bitcoinorama]

"This device is being designed in parallel by the ORSoC engineers and will offer industry leading performance and power consumption per GH.The final specifications for this device are being ironed out now but we can confirm the following.Minimum 175/350GH/s per device.28nm Standard ASICAn additional gain of 30% more hashing when the advanced algorithms provided by ORSoC are applied"

Those are the specs for the product that i bought, as advertized by KNC, and have gotten it verbally confirmed twice by both Sam and Marcus.
So that will be what i expect, and hold KNC to, come delivery time.

Dude you 100% were there when I was pressing Sam as to what milestones we should hold them to, I asked exactly that, and he pointed to the banner with the specs and said, "minimum 350gh/s, 28nm, September".   I have this all taped.

You also know if you've done your research, and/or followed this thread; Jupiter was 250gh/s originally and the 30% increase in hashing power was offered then. 250gh/s with a minimum of 30% is a minimum of 325gh/s. This falls totally inline with the 350gh/s promised as a +30% optimisation of 250gh/s.

Just looked over some old emails now, and the only message where I had touched on the subject that I can find easily I was referring as to whether Mars had been optimised at 6gh/s, or not, but come on anything over 350gh/s is crazy! If this is something that's going to make you walk away, you need to clear this up with him, so you can get a refund.

[J35st3r]

I mean, no chip testing methodology - just solder them to a board and see if they work?

Please prove that OrSoc & KNCMiner have no chip testing methodology. Links to posts where they say they are "employing no chip testing" would be sufficient.
Please provide citations for your statements in the future.

Since I've made several posts pointing this out, I'll help out here ...

Q&A

–
ChipGeek


3) Are you doing pre-package wafer test?

Marcus: No.

4) Are you doing post-packaging testing on a real production tester (Teradyne or similar)?

Marcus: No. We...and...and...I..I..I need to say a little bit about why; ah because we will have a self built in test that will automaically test...the...because the chips are so large, so that we can compensate for any losses in the Bitcoin engines. If there are any failing ones then we can compensate for that.

Me: Physically large?

Marcus: The...the die size of the...the?

Me: Yeah

Marcus: The die size will be...very large.

Me: But does that...ummm...

Marcus: That, that means that some of the parts in the ASIC might work and some will not, but we can compensate for that.

Another member: We can compensate for that.

Me: So does that mean you yield less per wafer?

Marcus: So yeah, you will always have a yield problem, and when you increase the die size, the yield problem becomes larger of course.

Me: ok

Possibly my post here was the origin of the "just solder chips on board" claim https://bitcointalk.org/index.php?topic=231739.msg2468261#msg2468261

And ChipGeek (who seems pretty knowledgeable on chip design) made the following observation https://bitcointalk.org/index.php?topic=232852.msg2474760#msg2474760

I don't want to get too trollsome on this point, just pointing out the source of the rumour.

[k9quaint]

I mean, no chip testing methodology - just solder them to a board and see if they work?

Please prove that OrSoc & KNCMiner have no chip testing methodology. Links to posts where they say they are "employing no chip testing" would be sufficient.
Please provide citations for your statements in the future.

Since I've made several posts pointing this out, I'll help out here ...

Q&A

–
ChipGeek


3) Are you doing pre-package wafer test?

Marcus: No.

4) Are you doing post-packaging testing on a real production tester (Teradyne or similar)?

Marcus: No. We...and...and...I..I..I need to say a little bit about why; ah because we will have a self built in test that will automaically test...the...because the chips are so large, so that we can compensate for any losses in the Bitcoin engines. If there are any failing ones then we can compensate for that.

Me: Physically large?

Marcus: The...the die size of the...the?

Me: Yeah

Marcus: The die size will be...very large.

Me: But does that...ummm...

Marcus: That, that means that some of the parts in the ASIC might work and some will not, but we can compensate for that.

Another member: We can compensate for that.

Me: So does that mean you yield less per wafer?

Marcus: So yeah, you will always have a yield problem, and when you increase the die size, the yield problem becomes larger of course.

Me: ok

Possibly my post here was the origin of the "just solder chips on board" claim https://bitcointalk.org/index.php?topic=231739.msg2468261#msg2468261

And ChipGeek (who seems pretty knowledgeable on chip design) made the following observation https://bitcointalk.org/index.php?topic=232852.msg2474760#msg2474760

I don't want to get too trollsome on this point, just pointing out the source of the rumour.

Excellent. I wanted the source of the material, not brontosaurus' warped view of it. Thank you for providing it.   

It sounds like KNC are not doing binning. They are confident that the yields will result in a low number of completely dead chips.
If they were making products with 1 or 2 chips on them, one completely dead chip would prevent that unit from being shipped as product.
Since there are a large number of chips per device, it is unlikely that 1 dead chip would make the device undeliverable.
Even 2-3 completely dead chips would still result in a partially functional product, it might not meet spec but it could sit in the corner at KNC and mine, it could serve as a test bed for firmware, etc.

Obviously, chip binning would increase the quality of the product but by how much we don't know. Perhaps spending time and money to get a 5% increase in quality is not worthwhile if they are beating their specs by 30%.
Time will tell.

Chip binning can be done post hoc, to screen out dead chips of there is an unforeseen yield problem.

[meowmeowbrowncow]

It's called trying to inflate the actual performance of your product and/or design knowledge. If your product is good, quote firm numbers based on hard, verifiable FACTS rather than allude to 'improvements' to a mathematical process which has data dependencies which cannot be changed or improved.

The academics who wrote the paper quoted are experts in their field - Dadda has an adder type named after him - and designed a method of reducing delay paths on an actual asic. They did'nt change or say they could change an algorithm. KNC claim to have an 'improved' algorithm, and that is just plain rubbish. Ask any mathematician.

Any respectable company would not make such ridiculous claims, if KNC have indeed used the methods from this paper in their design,then they should acknowledge it. Hence my annoyance.

Incidentally, Dadda and co. got their SHA256 engine to run at 'a clock speed of well over 1Ghz' on a 130nm process.

While typical SHA256 usage is for streaming encryption the fact that these scientists got a 1GHz clock rate is pretty impressive.


Whether this translates to a double SHA256 using nonce values - it may not.  This double SHA256 depends heavily on transistor density, which brings in to play all sorts of complications such as RI, voltage sag.


Bitfury's 'sea of hashers' approach might allow some use of this though.  Still, Bitfury is very competent, so he may have explored all options.

[keyzersoze]

"This device is being designed in parallel by the ORSoC engineers and will offer industry leading performance and power consumption per GH.The final specifications for this device are being ironed out now but we can confirm the following.Minimum 175/350GH/s per device.28nm Standard ASICAn additional gain of 30% more hashing when the advanced algorithms provided by ORSoC are applied"

Those are the specs for the product that i bought, as advertized by KNC, and have gotten it verbally confirmed twice by both Sam and Marcus.
So that will be what i expect, and hold KNC to, come delivery time.

Dude you 100% were there when I was pressing Sam as to what milestones we should hold them to, I asked exactly that, and he pointed to the banner with the specs and said, "minimum 350gh/s, 28nm, September".   I have this all taped.

You also know if you've done your research, and/or followed this thread; Jupiter was 250gh/s originally and the 30% increase in hashing power was offered then. 250gh/s with a minimum of 30% is a minimum of 325gh/s. This falls totally inline with the 350gh/s promised as a +30% optimisation of 250gh/s.

Just looked over some old emails now, and the only message where I had touched on the subject that I can find easily I was referring as to whether Mars had been optimised at 6gh/s, or not, but come on anything over 350gh/s is crazy! If this is something that's going to make you walk away, you need to clear this up with him, so you can get a refund.

I was there and and im not dissagreeing with you on that last statement bro. But the potentential "up to 30%" increase was to be on top of those figures. Thats why i made sure to ask twice. hence my "could be around 420?" in the transcripts. Thats what marcus and sam answered me any way. Maybe i missunderstood theyre answer or they missunderstood my qustion. But two positive answers, and the specs the way they are formulated on the website makes me somewhat confident that im right. But it is a "potential, up to 30% increase", thats why they didnt want to commit to any numbers more than 28nm 175/350, september.  Hence the "could" in the transcripts from both marcus and sam. Sounds in accordance with "Underpromise, overdeliver.

[J35st3r]

Excellent. I wanted the source of the material, not brontosaurus' warped view of it. Thank you for providing it.   

It sounds like KNC are not doing binning. They are confident that the yields will result in a low number of completely dead chips.
If they were making products with 1 or 2 chips on them, one completely dead chip would prevent that unit from being shipped as product.
Since there are a large number of chips per device, it is unlikely that 1 dead chip would make the device undeliverable.
Even 2-3 completely dead chips would still result in a partially functional product, it might not meet spec but it could sit in the corner at KNC and mine, it could serve as a test bed for firmware, etc.

Obviously, chip binning would increase the quality of the product but by how much we don't know. Perhaps spending time and money to get a 5% increase in quality is not worthwhile if they are beating their specs by 30%.
Time will tell.

Chip binning can be done post hoc, to screen out dead chips of there is an unforeseen yield problem.

Yeah, agreed. Though ChipGeek made the point that some chips will fail to a dead short across the power supply. These would have to be identified and the boards reworked. Hopefully a rare occurrence.

And just because there was no chip test strategy in place at the time of the Q & A, does not mean that KNCMiner are not working on one right now. Given that they had not yet finalised the foundry order at the time, perhaps chip testing was on the todo list to be worked on between tapeout and wafer delivery? An update on this would be useful.

[Bitcoinorama]

"This device is being designed in parallel by the ORSoC engineers and will offer industry leading performance and power consumption per GH.The final specifications for this device are being ironed out now but we can confirm the following.Minimum 175/350GH/s per device.28nm Standard ASICAn additional gain of 30% more hashing when the advanced algorithms provided by ORSoC are applied"

Those are the specs for the product that i bought, as advertized by KNC, and have gotten it verbally confirmed twice by both Sam and Marcus.
So that will be what i expect, and hold KNC to, come delivery time.

Dude you 100% were there when I was pressing Sam as to what milestones we should hold them to, I asked exactly that, and he pointed to the banner with the specs and said, "minimum 350gh/s, 28nm, September".   I have this all taped.

You also know if you've done your research, and/or followed this thread; Jupiter was 250gh/s originally and the 30% increase in hashing power was offered then. 250gh/s with a minimum of 30% is a minimum of 325gh/s. This falls totally inline with the 350gh/s promised as a +30% optimisation of 250gh/s.

Just looked over some old emails now, and the only message where I had touched on the subject that I can find easily I was referring as to whether Mars had been optimised at 6gh/s, or not, but come on anything over 350gh/s is crazy! If this is something that's going to make you walk away, you need to clear this up with him, so you can get a refund.

I was there and and im not dissagreeing with you on that last statement bro. But the potentential "up to 30%" increase was to be on top of those figures. Thats why i made sure to ask twice. hence my "could be around 420?" in the transcripts. Thats what marcus and sam answered me any way. Maybe i missunderstood theyre answer or they missunderstood my qustion. But two positive answers, and the specs the way they are formulated on the website makes me somewhat confident that im right. But it is a "potential, up to 30% increase", thats why they didnt want to commit to any numbers more than 28nm 175/350, september.  Hence the "could" in the transcripts from both marcus and sam. Sounds in accordance with "Underpromise, overdeliver.

Indeed, but that really would be some kind of voodoo, shamanic wizardry!!

[keyzersoze]

Next weeks update should hopefully end some of the speculations.*fingers crossed*
And set the scene for some new ones, i presume. 

[BenTuras]

Could it be that they are calculating with worse case scenario that about 23% of the cores in the chip will be dead, so the expected lowest hash rate in total is 350GH, with potentially 30% higher performance for all perfect chips ?
(in other words, 23% dead, 77% equals 350GH, and an unlikely 100% perfect chips will be 30% better, equals 455GH.)

[RoadStress]

Could it be that they are calculating with worse case scenario that about 23% of the cores in the chip will be dead, so the expected lowest hash rate in total is 350GH, with potentially 30% higher performance for all perfect chips ?
(in other words, 23% dead, 77% equals 350GH, and an unlikely 100% perfect chips will be 30% better, equals 455GH.)

I think it's hard to be that exact!

[titomane]

Could it be that they are calculating with worse case scenario that about 23% of the cores in the chip will be dead, so the expected lowest hash rate in total is 350GH, with potentially 30% higher performance for all perfect chips ?
(in other words, 23% dead, 77% equals 350GH, and an unlikely 100% perfect chips will be 30% better, equals 455GH.)

I'm not knc worker. But after visiting and ask Marcus and Sam. Their products have a 175-350Ghs hashrate. This hashrate includes all design improvements.
The devices can do OC under its buyer's responsibility. Loss of warranty.