Ultra-Low-Cost DIY FPGA Miner - 175MH/s @ $1/MH

[ArtForz]

... You need to build a 1.2V 5+A PSU and thats not easy and cheap. ...

Pretty easy if you use COTS DC/DC converter modules.
YV09T60 + input/output caps + 2kR 1% resistor = 12V->1.2V 60A, Vccint for 6 to 8 LX150.
For Vccaux and Vccio a small 12V or 5V->2.5V DC/DC, 3A is plenty for 8 LX150+controller if you only have JTAG and 100MHz SPI.
If you also need a few dozen mA @ 3.3V (for example for a USB transceiver), LDO from 5V or just grab it from the ATX psu.
Trivial to design+build on a 2-layer PCB or even protoboard.

[rph]

For the power supply, I'm using a TI PTV12010WAH at the moment,
$16 qty 1, 1.2V @ 8A, and it requires no external parts (aside from caps).
Wire it up and it works - no need to understand the black art of switching
regulator design.

I used a somewhat cheaper $10, 10A module on the carrier PCB.

This is indeed a pretty challenging + time consuming project, but there are
still a lot of people capable of building it. I hope to break the myth that the
BGA package requires expensive tools / professionals to assemble.

-rph

[rph]

Got the 6s25 miner working! 11.25MH/s @ 180MHz using 35% of the device. 0.605W.
Not exactly fast, but it validates the SW and MCU<->FPGA interface in preparation for the 6s150.

-rph

[eldentyrell]

If you aren't into DIY hot-plate soldering, you might be interested in this thread: https://bitcointalk.org/index.php?topic=45532

[deslok]

Got the 6s25 miner working! 11.25MH/s @ 180MHz using 35% of the device.
Not exactly fast, but it validates the SW and MCU<->FPGA interface in preparation for the 6s150.

-rph

Could you make a quick screen recording of that?

[rph]

It's been making money with the GPL'd mpbm code from TheSeven:



-rph

[deslok]

Wanted a video but that works just as well very impressed can't wait to see the 150 model running and hopefully buy some

[phorensic]

If you are getting 11MH/s on a 6s25, what is that going to scale up to on a 6s150?

[rph]

I'm up to 19.5MH/s in 6s25 -2, after working on it over the weekend.
It's mining for btcguild right now, drawing around 1W.

My 6s150 design meets timing at 156MH/s in 6s150 -3, and should easily
overclock to 175MH/s (1MH/$ at Avnet qty1 pricing). Might even reach 200MH/s
assuming the boards/ power supplies/cooling can handle that and keep it cool..
That would really reduce the gap b/t FPGAs and ATI GPUs.

Stay tuned..

-rph

[Keninishna]

hell yea I would buy a load of these. I'm pretty good at soldering my self and probably make some extra $$ reselling premade ones.

[rph]

Keep in mind that sales prices for fully assembled/tested boards will be ~$100
over the raw BOM costs. For a 100 FPGA cluster, that is like $10k..

Assuming things go well, that $20 skillet is going to save me a lot of money.

-rph

[ngzhang]

Some more details on the FGG484 BGA assembly:

Supplies
-------------
1. IR thermometer rated to 260C+ such as http://www.amazon.com/gp/product/B002YE3FS4
2. Electric skillet, like the one used in this Sparkfun tutorial: http://www.sparkfun.com/tutorials/59
3. No-clean flux syringe, such as Digikey SMD291-ND
4. Soldering iron [to pre-wet the PCB]

Calibration
---------------
1. Place an unpopulated PCB on the skillet, near the edge, directly over the burner coil.
2. Set the skillet to max.
3. Aim the IR thermo at the center of the PCB's BGA footprint and record temperatures every 15-30 seconds, as it heats to ~250-260C.
4. Plot the temp in Excel and compare with the IC mfg recommendations.
For Spartan6, that's http://www.xilinx.com/support/documentation/application_notes/xapp427.pdf.

If you're lucky the skillet will produce a good temperature profile on its own. The $20 Target skillet I bought 3 years ago
is almost perfect - just set it to max, and it will reach 250C after 4-5 minutes with a small PCB. It meets all of the Xilinx
guidelines, probably better than some professional assembly equipment. If it's way off, you might have to let everything cool down &
repeat a couple times with different setting. Or buy an MCU/Triac reflow controller. You don't have to match the temp profile
exactly, but obviously, the closer the better.

Assembly
---------------
With the profile set, I followed the prep instructions here: http://www.fpgarelated.com/usenet/fpga/show/39160-2.php
and monitored the FPGA with the IR thermo. Once the top of the case reached ~250C (~4 mins in)
I turned off the skillet, and used a fan to cool it down to ~100C over 4 minutes.



Checked it for power supply shorts, hand-soldered the bypass caps, then wired it up the LPCXpresso,
and it downloaded right way.

Sooner or later I will probably lose an FPGA through this process. But my bet is that it won't happen
often enough to justify the ~$50 per BGA fees for low-volume professional assembly.

-rph

LOL!

[rph]

Yeah, crazy, but it really works. 

-rph

[eldentyrell_old]

Got the 6s25 miner working! 11.25MH/s @ 180MHz

Wow, that is an amazing clock rate.  I understand that your code is based on the ztex miner with some changes to go from 128Mhz to 156Mhz+... any chance you'll release your changes?  I know you aren't required to...

[rph]

My code is full-custom VHDL, based on some good ideas in the ztex Verilog (which might or might not be
a derived work of the fpgaminer code, which is probably derived from some random guy's C code, etc).
I made enhancements for 2 cycles per SHA256 stage, and major changes to efficiently roll the core,
on smaller devices such as 6s25.

TBH I'm undecided on releasing full source. But ArtForz, ztex, and I have publically discussed the 6s150
optimizations in the ztex thread, and I released a snippet showing my changes for 2-cycles-per-stage,
so the concepts + optimization strategies are already public.

-rph

[vx609e]

Reading this.

[rph]

Got the carrier PCB!



It supports FPGA download & mining over micro-USB, with the on-board ARM Cortex-M3.
No need for a $200 JTAG probe.

If all goes well it'll be running the 6s150 in a couple days.

And then The Cluster begins.

-rph

[icvader]

Got the carrier PCB!

http://bitcoinfpga.com/pix/s6fg484-carrier-1.jpg

It supports FPGA download & mining over micro-USB, with the on-board Cortex-M3.
No need for a $200 JTAG probe.

Most importantly.. it'll finally let me run the 6s150..

-rph

Man that looks awesome; I have been following this thread from the first post. I am researching everything I can about building some of these myself. I am majoring in Computer Programming, unfortunately I am still in Gen Ed classes and haven't got to the good stuff yet. You are my Mr. Miyagi rph!

[heavyb]

on the real, if you get this working and can package it in some way to ship and plug and mine I will buy 5 right away, and more in the future.

[rph]

Just a quick update - I've started work on a new multi-FPGA carrier design.
Time to stop messing around, and build something badass.

-rph