Ultra-Low-Cost DIY FPGA Miner - 175MH/s @ $1/MH

[heavyb]

Just a quick update - I've started work on a new multi-FPGA carrier design.
Time to stop messing around, and build something badass.

-rph

something bad ass we can buy!

[icvader]

Just a quick update - I've started work on a new multi-FPGA carrier design.
Time to stop messing around, and build something badass.

-rph

The anticipation is palpable.

[jjiimm_64]

The anticipation is palpable.

agreed.....too bad all of my funds went towards gpus, I will have to wait for a while even after they are ready.

[grod]

Speculators paid me about $700 for the use of my 4 5830s in the past few months.   I'd be willing to throw some of that away on a similar project if only I thought I had the know-how.

[rph]

Thanks for all the comments guys. Dunno if I'm gonna productize/sell this stuff..
I'm doing it for fun, to sharpen my engineering skills and push the technology...
and of course to build a low-cost rig for myself..

ztex, big-chip-small-board, and the fpgaminer product are the best options ATM for fully assembled/tested HW

-rph

[icvader]

ztex, big-chip-small-board, and the fpgaminer product are the best options ATM for fully assembled/tested HW

-rph

Those guys are all really on to something for the end users; but for people like myself, who have at least some hardware knowledge and feel confident taking risks, I would gladly pay you for comprehensive build guide.

[godofal]

ztex, big-chip-small-board, and the fpgaminer product are the best options ATM for fully assembled/tested HW

-rph

Those guys are all really on to something for the end users; but for people like myself, who have at least some hardware knowledge and feel confident taking risks, I would gladly pay you for comprehensive build guide.

+1

im good @ soldering, and confident in hacking stuff
but building something this complex without a guide? no can do

i bet that a build guide would sell pretty good

[ngzhang]

ztex, big-chip-small-board, and the fpgaminer product are the best options ATM for fully assembled/tested HW

-rph

Those guys are all really on to something for the end users; but for people like myself, who have at least some hardware knowledge and feel confident taking risks, I would gladly pay you for comprehensive build guide.

+1

im good @ soldering, and confident in hacking stuff
but building something this complex without a guide? no can do

i bet that a build guide would sell pretty good

good @ BGA soldering? pretty good.

[gopher]

Just a quick update - I've started work on a new multi-FPGA carrier design.
Time to stop messing around, and build something badass.

-rph

rph, great work, I have finally find courage to subscribe to this thread...

I have couple of comments/suggestions.

Have you though of adding ETH PHY and SD card modules to the carrier board so once the bit-stream is uploaded (written on the SD), the unit could be set to survive hardware reset and run fully autonomously?

I am sure implementing compact TCP/IP stack and HTML server on the FPGA would not be that difficult (many available open source examples out there), and the required Bitcoin function, to feed the hashes to the FPGA and then feed the result back to a pool, should be relatively easy to code, re-write one of the better Python miner-scripts.

Also, with regards to the efficiency of the core - correct me if I understand this wrong - I see that professional outlets achieve 2.4 Gh/s with a Spartan 6 -3 (at least that is what I conclude after reading the document posted here http://www.heliontech.com/downloads/fast_hash_xilinx_datasheet.pdf#view=Fit - and that is way more efficient compared to the various FPGA implementations discussed on the bitcointalk.

Otherwise - the mere fact that you guys already achieved capital cost of $1/Mh in single chip quantities (that's what my highly-cost-optimised GPU rigs cost me, in QTY>10) indicates that you are on the right track - and things can only improve from here.

[jjiimm_64]

Just a quick update - I've started work on a new multi-FPGA carrier design.
Time to stop messing around, and build something badass.

-rph

rph, great work, I have finally find courage to subscribe to this thread...

I have couple of comments/suggestions.

Have you though of adding ETH PHY and SD card modules to the carrier board so once the bit-stream is uploaded (written on the SD), the unit could be set to survive hardware reset and run fully autonomously?

I am sure implementing compact TCP/IP stack and HTML server on the FPGA would not be that difficult (many available open source examples out there), and the required Bitcoin function, to feed the hashes to the FPGA and then feed the result back to a pool, should be relatively easy to code, re-write one of the better Python miner-scripts.

Also, with regards to the efficiency of the core - correct me if I understand this wrong - I see that professional outlets achieve 2.4 Gh/s with a Spartan 6 -3 (at least that is what I conclude after reading the document posted here http://www.heliontech.com/downloads/fast_hash_xilinx_datasheet.pdf#view=Fit - and that is way more efficient compared to the various FPGA implementations discussed on the bitcointalk.

Otherwise - the mere fact that you guys already achieved capital cost of $1/Mh in single chip quantities (that's what my highly-cost-optimised GPU rigs cost me, in QTY>10) indicates that you are on the right track - and things can only improve from here.

if your refering to  "max SHA-1 rate 2041 Mbps 1542 Mbps 2578 Mbps"


I am not sure if Mbps equates to Mhash/s .  first I dont know if they mean Mega bytes per sec, or mega bits per sec, but it is definitely not mega hashes per sec.

Please someone jump in here who knows...  because this helion chip would be HUGE>

[gopher]

No, in the table, in the "Max SHA256 rate" for "Spartan-6 -3" indicates 1,225 Mbps and elsewhere at that site, they claim "one clock per algorithm round" - I am calculating that if one hash is 512 bytes then 1,225 / 0.5 = 2,392 Mhash/sec.

[EDIT] Wait a minute - I think I found my mistake  - the hash is in bytes and the bandwidth is in Mbps - which means I should divide the 2,392 by 8 - still 299 Mhash/s - much better than what we see in these forums.

[EDIT AGAIN] I not very good with these bits/bytes, but from this source http://www.s2cinc.com/product/pd.asp?id=278 it looks like the hash is actually 512 bits, hence the original calculations apply and the performance would stand at 2,392 Mhash/sec.

[DeathAndTaxes]

No, in the table, in the "Max SHA256 rate" for "Spartan-6 -3" indicates 1,225 Mbps and elsewhere at that site, they claim "one clock per algorithm round" - I am calculating that if one hash is 512 bytes then 1,225 / 0.5 = 2,392 Mhash/sec.

[EDIT] Wait a minute - I think I found my mistake  - the hash is in bytes and the bandwidth is in Mbps - which means I should divide the 2,392 by 8 - still 299 Mhash/s - much better than what we see in these forums.

[EDIT AGAIN] I not very good with these bits/bytes, but from this source http://www.s2cinc.com/product/pd.asp?id=278 it looks like the hash is actually 512 bits, hence the original calculations apply and the performance would stand at 2,392 Mhash/sec.

Not quite.

1225 Mbps = 1,225,000,000 bit/s.  1 SHA256 hash is 512 bits.
1225 Mbps = 1,225,000,000 bit/s / 512 = 3,392,578 hashes/s.  
1225 Mbps = 2.4 MH/s  However bitcoin algorith requires 2 hashes not 1 hash per bitcoin hash.  So that's 1.2 MH/s.

That number is still likely high because they are showing streaming performance (where key in static) and you are streaming huge amounts of data through the chip.  Bitcoin doesn't work that way so you have the setup and takedown overhead on each hash.  Likely performance for bitcoin applications would be 10% to 20% lower.

I have looked most FPGA commercial designs are optimized for streaming (massive input and output to hash large amounts of data).  Totally outclassed by any FPGA design prototypes on bitcointalk.

Edit: fixed math.

[rph]

The VHDL/Verilog guys in this community are top-notch and are getting results way
beyond what's possible with general-purpose SHA256 cores.

In Mbps terms, my design is around 159,744 Mbps [2 SHA256 cores * 512 bits per hash * 156 MH/s].

That 2041Mbps core is 2041/(512*2)= 1.99MH/s. You could fit maybe 30-50 of them in 6s150.

-rph

[rph]

I am sure implementing compact TCP/IP stack and HTML server on the FPGA would not be that difficult

It's possible but takes engineering time, and FPGA resources away from the miner.
Better to use a $3-4 USB microcontroller IMO. Or a $10 ethernet MCU if you really, really need
a standalone device. But I prefer using a $50 Atom PC to connect USB FPGA miners to the net.

PCs are cheap and most people here have one running 24/7 anyway.

-rph

[heavyb]

still looking to buy a few of these!

[kloinko1n]

1225 Mbps = 1,225,000,000 bit/s.  1 SHA256 hash is 512 bits.
1225 Mbps = 1,225,000,000 bit/s / 512 = 3,392,578 hashes/s.  
1225 Mbps = 2.4 MH/s  However bitcoin algorith requires 2 hashes not 1 hash per bitcoin hash.  So that's 1.2 MH/s.

1,225,000,000 bit/s / 512 = 3,392,578 2,392,578 hashes/s. 

 

[rph]

And a Bitcoin "hash" is really sha256(sha256(x)). So when most devs here say 120MH/s it
really means 240 million SHA256 computations per second.

Each SHA256 hash covers 512 bits of data. So, as you guys have said:

To convert "Mbps" to "Bitcoin MH/s" divide by 1024.
To convert "Bitcoin MH/s" to "Mbps" multiply by 1024.

-rph

[helloworld]

And a Bitcoin "hash" is really sha256(sha256(x)). So when most devs here say 120MH/s it
really means 240 million SHA256 computations per second.

Each SHA256 hash covers 512 bits of data. So, as you guys have said:

To convert "Mbps" to "Bitcoin MH/s" divide by 1024.
To convert "Bitcoin MH/s" to "Mbps" multiply by 1024.

-rph

So when people talk about Deepbit or the entire network for example, do they mean bitcoin hashes or sha256 hashes?

[Valalvax]

Bitcoin Hashes

Now when they talk about it compared to... Folding for example

I'd have to assume SHA256

[DeathAndTaxes]

1,225,000,000 bit/s / 512 = 3,392,578 2,392,578 hashes/s. 

I was framed I tell you.  Someone must have moved my 2 key.  Seriously that happens a lot w/ me.  My brain is computing faster than the I/O bus can handle the data stream.