Open Source Bitcoin ASIC miner project that uses 2x BM1387 (Antminer S9)

[developeralgo]

Finally ordered the PCB fab plus Assembly plus Stencil , ESP32-C3_devkitC-02U and BM1397AG chip. i will wait for everything to be delivered in 3 weeks before starting to test the hell out of it.

For Skot, Have you tested the TPS40305 power delivery  with BitaxeMax single chip yet? will it be part of a single complete board or  an Add-on daughter board ?

That's awesome, I'm excited to have you working on this as well!

I just got the first TPS40305_supply board put together today, and It seems to be working! I haven't tried it out under load yet, and I haven't put together a BitaxeMax yet. Hopefully that will happen this week, I'll keep you posted.

Fantastic , that's good news about TPS40305_supply board . Let's us know after load test. i was in the process of ordering a few to test with bitaxeMax

[Skot]

Nonce or Skot ,  For the assembly of the top of bitaxeMax  that includes ESP32-C3-Devkit and BM1397AG chips  do you guys personally solder them by hand or you use an assembly service to do it. I am looking for a way to streamline the Complete parts order (Except the BM1397) at JLCPCB or PCBWAY or etc

1. Order all parts on JCLPCB or PCBWAY or any other fab house ( both JLCPCB/PCBWAY inventory and external globally sourced) --Note: Globally sourced parts are ordered by the Fab house and shipped to them for your assembly work.
2. Wait for all globally sourced parts required for the bitaxeMax board assembly to arrive at the Assembly factory (JLCPCB / PCBWAY  / others)
3. Place an order for PCB Fabrication with Assembly Service and choose or use the global pre-ordered parts that are now available for this  assembly work
4. Have the completed assembled boards shipped  for the final assembly of BM1397 chips on it ( Skot or Nonce -- do you know any assembly service that can do BM1397 chips & ESP32-C3-DevKitC-02 assembly in North America ? )
5. Test all the boards


i am trying to see if its possible to streamline every process to lower the costs as much as possible so that its affordable even at lower volume e.g 5 , 10 or even 50 fully assembled boards. if we can get the each complete production board cost below let's say below $50 or $60 or $70 or $80 not including taxes, duty and shipping that would fantastic. The lower the price & power consumption the better

For prototypes in ~QTY5 or less I assemble them myself. I order the PCBs and stencils for each side from China via Seeed, PCBWay, or JLCPCB. I use the stencil to put leaded solder paste on the PCB, then populate the parts with tweezers. Then I reflow the PCBs in a (dedicated) convection toaster oven with a thermocouple temperature probe. It actually works really well once you get the hang of it. There are plenty of Youtube videos covering these techniques if you want to give it a try.

If there are more than 5 boards, or the board is more complex I usually get them assembled by a short run fab. I've used a couple in Silicon Valley, CircuitHub in MA and PCBWay in China.

I'm sure any PCB assembly fab can physically solder the BM1397. If they can't figure out how to source them, we can consign the parts. We don't need to assemble the ESP32-C3-DevKitC-02. The dev kits are just for prototyping. Once things are locked down we can switch to using the ESP32-C3-WROOM-02 modules directly. The fab will be able to source those.

[Skot]

Finally ordered the PCB fab plus Assembly plus Stencil , ESP32-C3_devkitC-02U and BM1397AG chip. i will wait for everything to be delivered in 3 weeks before starting to test the hell out of it.

For Skot, Have you tested the TPS40305 power delivery  with BitaxeMax single chip yet? will it be part of a single complete board or  an Add-on daughter board ?

That's awesome, I'm excited to have you working on this as well!

I just got the first TPS40305_supply board put together today, and It seems to be working! I haven't tried it out under load yet, and I haven't put together a BitaxeMax yet. Hopefully that will happen this week, I'll keep you posted.

Fantastic , that's good news about TPS40305_supply board . Let's us know after load test. i was in the process of ordering a few to test with bitaxeMax

I definitely imagine the power supply being incorporated on the bitaxe PCB. Assuming the TPS40305 works, I'm going to move it onboard and make it adjustable from the ESP32 using something like the Maxim DS4432. Adjusting the ASIC core voltage and clock frequency while monitoring the temperature, hashrate and power consumption is how you "tune" the miner for best performance.

[NotFuzzyWarm]

I definitely imagine the power supply being incorporated on the bitaxe PCB.

Um for god's sake yes!!!
I think I had posted a few links about feeding the chips earlier in the thread... How power is fed to an ASIC, FPGA, CPU, or any other high-power high-speed switching device is a critical design point that is easily overlooked. In short the PDN (Power Delivery Network) is NOT just a simple DC bus - it must be treated as a RF stripline due to the sub-microsecond high current spikes that happen with every clock cycle...

edit: It was in your thread in the Development & Technical area:
A good place to start for resources is TI.
https://www.ti.com/design-resources/design-tools-simulation/processor-fpga-power/overview.html
https://www.ti.com/design-resources/design-tools-simulation/power-stage-designer.html

New goodies:
A good paper on it available through ResearchGate

From the EDN archives: https://www.edn.com/debugging-approach-for-resolving-noise-issues-in-a-pdn/
 and very good presentation about it with a very simple test circuit https://www.edn.com/pdn-issues-occur-in-the-simplest-of-circuits/  In that article figures 3 & 4 along with accompanying text clearly shows the problem and that's using a 5v device. ASICs with their <1v Vcore, well...
Results from search of the EDN archives re: PDN's  
All are highly recommended reading.

[developeralgo]

Later once we have ironed out everything, if we can source every part cheaply i have a long-term PCB manufacuring relationship with a few PCB Fab houses in China, HK & Taiwan , i can offer to manufacture everything at volume for an affordable cost for the community or each member can have it done themselves. Or if you have a different option , chime in , that would be great.

Absolutely! That sounds like a great idea. What kind of quantity does it make sense to start at with your fab?

In order to lower the 2 major costs associated with fabrication and assembly to an affordable and acceptable entry level for the community on

1. Material / parts
2. Assembly

we need to order the parts in bulk and fabricate for the community in batches . Let's say we start with 50 or 100 complete units and then slowly increase to 200 or 500 or 1000 complete units per batch depending on demand from the community. Normally ordering small/tiny parts on a Reel is much cheaper than a Tape cut. A reel contains usually 1000 or 10000 for very tiny pieces , 100 or 1000 for medium but still slightly small pieces.

Once you add test TPS40305 power delivery to the board PCB, schematic, Gerber files, i will order the next prototype batch of 5 so that we can test it quickly. if you DM me i can send you a few pieces of that batch for testing.
 

[Skot]

I think I had posted a few links about feeding the chips earlier in the thread... How power is fed to an ASIC, FPGA, CPU, or any other high-power high-speed switching device  is a critical design point that is easily overlooked. In short the PDN (Power Delivery Network) is NOT just a simple DC bus - it must be treated as an RF stripline due to the sub-microsecond high current spikes that happen with every clock cycle...

edit: It was in your thread in the Development & Technical area:
A good place to start for resources is TI.
https://www.ti.com/design-resources/design-tools-simulation/processor-fpga-power/overview.html
https://www.ti.com/design-resources/design-tools-simulation/power-stage-designer.html

New goodies:
A good paper on it available through ResearchGate

From the EDN archives: https://www.edn.com/debugging-approach-for-resolving-noise-issues-in-a-pdn/
 and very good presentation about it with a very simple test circuit https://www.edn.com/pdn-issues-occur-in-the-simplest-of-circuits/  In that article figures 3 & 4 along with accompanying text clearly shows the problem and that's using a 5v device. ASICs with their <1v Vcore, well...
Results from search of the EDN archives re: PDN's  
All are highly recommended reading.

This is amazing, thanks NotFuzzyWarm! I’ll definitely check this out. Gotta watch those radiated emissions.
How close do you think an Antminer is to passing a Part 15 EMC test?! 

[NotFuzzyWarm]

How close do you think an Antminer is to passing a Part 15 EMC test?

I'd be surprised if it does not pass as a Class-B device.

The main point about the RF design aspects of feeding these chips is not so much about cutting down EMI as it is about making sure that the Vcore at the IC pads stays within very tight limits as the clock cycles the gazillions of logic gates in the chip on/off all at the same time.

Remember, unlike a CPU or GPU chip whose various circuits are 'doing their own thing' which includes waiting for data to be passed to/from other areas, in a mining ASIC all of the logic gates in the chip operate in lock-step with every clock cycle. 1 cycle to load data into logic array (cores) from coms buffer (and present result from previous data to coms buffer), 1 cycle to push data through array, rinse & repeat with several thousand logic cores running at several hundred MHz. As a result, the PDN needs to be 'tuned' so to speak to smooth out the resulting current spikes and corresponding voltage dips. That said, since a mining ASIC has very predictable operations going on with no buffering or wait-states involved (aside from in the coms) on vs a CPU/GPU it is much simpler/easier to address the issue.

As pointed out in that 'simple circuit' article, even with the bypass cap located very close to the chip there is still a sizeable difference in ripple voltage seen at the cap vs at the chip's power pads. That test circuit gave them 89mv ripple at the cap but 1V ripple at the chip located just a few mm away from the cap. Even for a 5v device that is pushing things - 1v is 20% of 5v. Apply that potential 20% ripple to a circuit running at <1v will definitely cause problems because the switching thresholds are far tighter.

Edit: When I started in this Forum in early 2014 I did a fair bit of forensics on the CoinCraft miner from the Swiss company Bitmine.ch (now out of business) that used the A1 chip which Innosilicon designed for them, more precisely their "Made in USA" miner that they 'partnered' with AMT to make & sell here in the USA. Exact-same miner, just with parts sourced, PCB's (using Bitmine's gerber files & BOM's) made by and the miners assembled by the US company IMET. A very large part of their problem was due to absolutely clueless design of the PDN on their hash boards. 2nd issue was Bitmine having absolutely no idea about the proper thermal design that the chips required, 3rd was IMET's lack of experience in dealing with high power chips & the needed *very* thick power planes & thermal vias to move heat leading to innumerable issues...

Even Inno repeatedly pointed out the errors but the Powers-That-Be ignored their advice with disastrous consequences. OTOH, the company that did the famous DragonMiner (not to be confused with the far later DragonMint) that used the exact same A1 ASIC knew how to do things right and produced 1 damn fine miner.

A good start about the Bitmine.ch/AMT kerfuffle starts here and here I'll try to dig up more of those threads that in summary are Poster Child example of how to totally screw a miner design.

Last edit: I guess to summarize this, ja, you *can* use a separate Vcore PSU along with heavy bus cable to feed the hash board like the large miners do with bus bars but remember they are pushing much much higher voltages through long strings of chips. Pushing just a few hundred mv at up to 20A through the cables is not so forgiving. That said, just as the large miners do, the most important bit is to properly address the quality of power presented to each chip and not just to what is fed to the power input planes of the board.

[developeralgo]

How close do you think an Antminer is to passing a Part 15 EMC test?

I'd be surprised if it does not pass as a Class-B device.

The main point about the RF design aspects of feeding these chips is not so much about cutting down EMI as it is about making sure that the Vcore at the IC pads stays within very tight limits as the clock cycles the gazillions of logic gates in the chip on/off all at the same time.


Edit: When I started in this Forum in early 2014 I did a fair bit of forensics on the CoinCraft miner from the Swiss company Bitmine.ch (now out of business) that used the A1 chip which Innosilicon designed for them, more precisely their "Made in USA" miner that they 'partnered' with AMT to make & sell here in the USA. Exact-same miner, just with parts sourced, PCB's (using Bitmine's gerber files & BOM's) made by and the miners assembled by the US company IMET. A very large part of their problem was due to absolutely clueless design of the PDN on their hash boards. 2nd issue was Bitmine having absolutely no idea about the proper thermal design that the chips required, 3rd was IMET's lack of experience in dealing with high power chips & the needed *very* thick power planes & thermal vias to move heat leading to innumerable issues...

Even Inno repeatedly pointed out the errors but the Powers-That-Be ignored their advice with disastrous consequences. OTOH, the company that did the famous DragonMiner (not to be confused with the far later DragonMint) that used the exact same A1 ASIC knew how to do things right and produced 1 damn fine miner.

wow!! that's a great advice in power delivery design for mining chips

Since you have experience with Mining chip power delivery systems , can you help skot and community with power delivery system so that all of us can benefit from your long-term experience.

[NotFuzzyWarm]

Since you have experience with Mining chip power delivery systems , can you help skot and community with power delivery system so that all of us can benefit from your long-term experience.

Nope.
8 years ago when I 1st got into mining and joined here I might have but not these days. Going on 67 years old, just don't have the energy to do side projects anymore. After getting home from work (R&D Engineer at LaserMech) it's just eat dinner, go online for a couple hours and then bed time...

That said, those links to EDN articles about PDN design considerations pretty much cover everything giving valuable pointers about what to keep in mind when laying out the power traces to the chip(s), how to calculate the inductance of said traces, and calculate good ball-park values for the bypass caps (located as close as possible to the chips power pads) to minimize the Vcore bounce.

If anything, just take care with the layout and have a variety of bypass caps with different values you can tack onto the board and experiment with to produce the lowest amount of ripple seen at the chip power pads. Again it must be emphasized to not only place the 'scope probe on the Vcore pad but also attach the 'scope return lead to the chip power return pad. Um, I should add that the 'scope MUST have an ungrounded probe return! These days most do along with the multi-trace 'scopes having each channel return isolated from each other as well as from chassis ground. Connecting the return anywhere else introduces artifacts caused by the high frequency currents flowing through the power planes.

It's not difficult to get right or even 'good enough', it's just that it's too easy for folks to not give the matter a 2nd thought and just use a good ol' 0.1mfd cap stuck nearby the chip, leave it at that, then wonder why the circuit is glitchy. As a bonus it would be a good lab experiment for you to see the effects of looking at the voltages not only at the chip but also at various random points on the power planes. Tip: Use the 'scope set to AC input mode, it will let you turn up the gain to have a good view of the ripple voltages. Most newcomers to the high-speed power circuit design world are astonished at how different things look when probing at various locations on a solid power plane - as I've said elsewhere, this is not a simple DC bus feeding a static load or even one using devices with (in comparison) slow switching times. It acts like a DC-biased RF power circuit.

Edit: For a good in-depth look into the 'joys' of miner design, I highly recommend the Bitmine CoinCraft A1 28nm chip distribution / DIY support thread thread. It is about doing the exact same thing you are doing - a community -designed, open source miner - but using the A1 chip. That thread also drifts into a couple other community-miner design projects that were going on in the early days. That thread was of immense help when I did the forensics for AMT on the (Bitmine.ch) miner they were trying to produce. In short it covered everything that killed the Swiss design so I had a good idea what to look at. The lead designer in the thread even let Bitmine know what to do and the company ignored them. Oops...

Last edit: About the bypass caps. Note the plural. Best practice is to use several different value caps in parallel to get the final total capacitance needed. Usually 2 is fine with a small one 1/10th the size of a big one. 3 caps is even better. That allows each cap to target different parts of the wide range of harmonics the spike produce.

[Skot]

Edit: For a good in-depth look into the 'joys' of miner design, I highly recommend the Bitmine CoinCraft A1 28nm chip distribution / DIY support thread thread. It is about doing the exact same thing you are doing - a community -designed, open source miner - but using the A1 chip. That thread also drifts into a couple other community-miner design projects that were going on in the early days. That thread was of immense help when I did the forensics for AMT on the (Bitmine.ch) miner they were trying to produce. In short it covered everything that killed the Swiss design so I had a good idea what to look at. The lead designer in the thread even let Bitmine know what to do and the company ignored them. Oops...

Wow, that's a trip to see that old development thread.

0.85BTC per chip (25GH). At $150/BTC, that's $127.50 per 25 GH, or $5.1/GH

Those ASICs were expensive!

[developeralgo]

Wow, that's a trip to see that old development thread.

0.85BTC per chip (25GH). At $150/BTC, that's $127.50 per 25 GH, or $5.1/GH

Those ASICs were expensive!

Agree !!!!! that was extremely expensive for that to survive. Currently  New BM1397 @$20/chip @ 300GH/s  @ 20W = approx  $0.067/GH @ 15GH/W

[developeralgo]

skot, have you managed to test the load on the TPS40305 Power delivery board that you got ? if yes, have you by any chance managed to update the schematic / pcb for a combined single board with 2 or 4 chips considering what the Notfuzzywarm mentioned about high ripple across the power plane.

[Skot]

skot, have you managed to test the load on the TPS40305 Power delivery board that you got ? if yes, have you by any chance managed to update the schematic / pcb for a combined single board with 2 or 4 chips considering what the Notfuzzywarm mentioned about high ripple across the power plane.

Just got the bitaxeMax (single BM1397) setup today and started testing with the TPS40305_supply board.. It works!

here is an exciting line from cgminer:
0: GSF 3NNU10x0: BM1397:01+ 445.00MHz T:600 P:311 (28:14) | 66.1% WU: 65% | 174.6G / 151.9Gh/s WU:2122.0/m

I was playing around with the core voltage a bit and the TPS40305 seemed to be able to handle 17 Watts. The mosfets and inductor definitely got warm, but not hot.

I forgot to pull the enable line on the bitaxe 25MHz oscillator high. once I air wired that, everything came alive. https://github.com/skot/bitaxe/issues/9

I'm in between oscilloscopes at the moment, so it will be a bit before I can try NotFuzzyWarm's tip to measure the core voltage ripple at the ASIC.

[developeralgo]

skot, have you managed to test the load on the TPS40305 Power delivery board that you got ? if yes, have you by any chance managed to update the schematic / pcb for a combined single board with 2 or 4 chips considering what the Notfuzzywarm mentioned about high ripple across the power plane.

Just got the bitaxeMax (single BM1397) setup today and started testing with the TPS40305_supply board.. It works!

here is an exciting line from cgminer:
0: GSF 3NNU10x0: BM1397:01+ 445.00MHz T:600 P:311 (28:14) | 66.1% WU: 65% | 174.6G / 151.9Gh/s WU:2122.0/m

I was playing around with the core voltage a bit and the TPS40305 seemed to be able to handle 17 Watts. The mosfets and inductor definitely got warm, but not hot.

I forgot to pull the enable line on the bitaxe 25MHz oscillator high. once I air wired that, everything came alive. https://github.com/skot/bitaxe/issues/9

I'm in between oscilloscopes at the moment, so it will be a bit before I can try NotFuzzyWarm's tip to measure the core voltage ripple at the ASIC.

Sweet line and great progress. I checked the TPS40305 reference design on TI website with WEBENCH Designer  even with an EMI filter added and lowest Ripple on the power plane , i could only simulate it pulling out  total power of 18W. So at 17W then you must be almost at Max for that buck converter.

Did you get it anywhere above 300 GH/s in your test? Can Maxim Voltage adjuster  be used to push it above 300 GH/s ?

[n0nce]

~

Fuzzy! You legend! Thanks for all this information again.. It makes total sense.

Due to limited time I may just quickly order some BitaxeMAX boards and probe around those with my scope; I feel like getting my breakout board to run is pointless after the insane progress lately, made by Skot.
Hopefully I can contribute more by analyzing his latest boards and checking what can be improved.

[NotFuzzyWarm]

~

Fuzzy! You legend! Thanks for all this information again.. It makes total sense.

Due to limited time I may just quickly order some BitaxeMAX boards and probe around those with my scope; I feel like getting my breakout board to run is pointless after the insane progress lately, made by Skot.
Hopefully I can contribute more by analyzing his latest boards and checking what can be improved.

Just passing on the Ancient Wisdom accumulated over the many many decades of doing the Voodoo that I do so well...
They just do not teach that stuff in schools any more und unless one interns under the right mentors well...

[sidehack]

I'm not sure how much worse it is now but when I finished my EE/CpE over a decade ago, half my senior design class had never used a soldering iron, and that's at one of the best engineering schools in the midwest (usually ranked #1 when comparing quality versus price). It's definitely disappointing how much hands-on stuff isn't being taught.

[developeralgo]

~

Fuzzy! You legend! Thanks for all this information again.. It makes total sense.

Due to limited time I may just quickly order some BitaxeMAX boards and probe around those with my scope; I feel like getting my breakout board to run is pointless after the insane progress lately, made by Skot.
Hopefully I can contribute more by analyzing his latest boards and checking what can be improved.

i finally got the initial BM1397 bitaxeMax boards that i ordered and started assembly. Hope to test it this coming week. Also working from the BitaxeMax4 schematic that skot has updated to see if i can add power delivery system with an EMI filter or  Maxim DS4432 on the board

[Skot]

i finally got the initial BM1397 bitaxeMax boards that i ordered and started assembly. Hope to test it this coming week. Also working from the BitaxeMax4 schematic that skot has updated to see if i can add power delivery system with an EMI filter or  Maxim DS4432 on the board

Thats awesome! There is one goof (that I've found so far) on the R1 PCBs. Should be an easy bodge wire fix; I put details in the GitHub issue; https://github.com/skot/bitaxe/issues/9

lemme know if you have questions..

[developeralgo]

i finally got the initial BM1397 bitaxeMax boards that i ordered and started assembly. Hope to test it this coming week. Also working from the BitaxeMax4 schematic that skot has updated to see if i can add power delivery system with an EMI filter or  Maxim DS4432 on the board

Thats awesome! There is one goof (that I've found so far) on the R1 PCBs. Should be an easy bodge wire fix; I put details in the GitHub issue; https://github.com/skot/bitaxe/issues/9

lemme know if you have questions..

i checked out the R1 PCB which is what i have. Did you update that wire from TP10 to TP1  in the Kicad PCB on github yet ? probably rename the PCB to R2 after update

Skot,What kicad plugin do you use for Auto routing and placement on the PCB from bitaxeMax4 schematic ? Is there an easier way than updating and doing placement and routing manually ? i usually use Freerouting plugin in Kicad. Maybe there is a better way ? i know Altium and other CAD software do have such plugins.