Block Erupter: Dedicated Mining ASIC Project (Open for Discussion)

[Lethos]

What this thread is entirely missing is where the production would be done. (masks, wafers, packaging and bonding). And some really good explanation of why it would be so cheap.
No "LOL we are in China" is not sufficient.

Which software is used to design the chips? Where do the models for the gates come from?

FYI: I am almost certain this is a scam.

There is more details being provided here than anything BFL is doing (and historically provides) I know you don't like them either, so for that I believe them more than them. It might not say much, but it's understandable when doing new things in your field you can't go telling everyone everything, without needing to have those answered in confidence.
Maybe not all your questions are answered, but their is a fair amount in the first post (updated) as well as scattered through out the thread, as well as friedcat answering the more techy questions you wanted with your accusation of being a scam.

They are formed in the city of Shenzhen (China), which has a well known technology manufacturing background, many of the "big boys" in tech in china are based in that city. It's slightly more specific than somewhere in china, don't forget a good portion of electronics today are made there, and with it being done on 130nm (old now) it's ideal for their first design chip. Every question the community has asked, he has managed to give a good open answer, his reputation is far better than BFL right now.

[Carlton Banks]

his reputation is far better than BFL right now.

I think that's a little unfair on BFL. They have shipped hardware, not particualry successfully, but they're in a bit of an awkward position being first to market (albeit pre-orders). How would you do it?

It's very difficult to do a direct comparison between the two, as their operating models are so very different. Like I said, I prefer the Bitfountain model overall, but that will be completely irrelevant if Bitfountain don't succeed. Under those circumstances, Block Eruptor cheerleaders will be purchasing their units from a parallel universe

[Lethos]

his reputation is far better than BFL right now.

I think that's a little unfair on BFL. They have shipped hardware, not particualry successfully, but they're in a bit of an awkward position being first to market (albeit pre-orders). How would you do it?

It's very difficult to do a direct comparison between the two, as their operating models are so very different. Like I said, I prefer the Bitfountain model overall, but that will be completely irrelevant if Bitfountain don't succeed. Under those circumstances, Block Eruptor cheerleaders will be purchasing their units from a parallel universe

It's not unfair, how many exact details do you know about the new ASIC product from BFL? Outside of the PR stunt provided info, that already has a lot of speculation surrounding how they will manage those numbers. How far off was the first BFL stated numbers for their singles; massively off because they were guessing. Lab work and predictions based on real numbers didn't factor into it.

Now compare that to what Friedcat has provided that about his. Big difference, he has been more open and provided more answers. They are providing numbers and info from the lab as it comes. It's the same reason why I supported Yohan (enterpoint), they are honest and open and discuss their product. Customer support comes first with these people it makes a difference.

BFL could have been more open from the start like other FPGA developers, they choose not to, it still hasn't changed, Inaba might change this, but it's early days. I however don't think one person can pull it off, if it stems further up the chain.

... sorry to derail your thread Friedcat.

[Carlton Banks]

It's not unfair,

sigh

It helps if you read and comprehend what I actually said. Oh well.

[Lethos]

It's not unfair,

sigh

It helps if you read and comprehend what I actually said. Oh well.

Just because I am critical of your trying to badly defend them based on the difficulty of being the first to market you think I didn't read it? Yes there is many people who could of done it better and given the chance I'm sure they will prove it. I've been a consultant and developer quiet a while, so yeah customer support wise I would of done a lot better job than they did. But it's not my area of speciality, so I support those who's speciality it is and do a good job that aspect.

Of course did read, but it's not an good excuse to use (first market mistakes). It would maybe held up better if they hadn't continued to act the same way with later products. By the fact you keep quoting just a tiny portion of what I say, I could be childish and accuse you of the same (not reading/comprehending). But will it get me anywhere not really.

I am happy BFL finally has a competitor that stands a chance of beating it to market this time.

[Carlton Banks]

Oh dear! I do not know how to reply, based on my assessment of the way you appear to think. I promise not to stand up for what I believe to be the case in the future, you've totally convinced me of that.

NOTE: I'm strongly in favour of competition between ASIC hardware developers, as the market competition will go a long way to ensure that unit price and overall hardware qualities will be favour the customers as much as the vendor. Anyone in the market for a SHA-2 ASIC would be crazy to believe otherwise

[tucenaber]

What this thread is entirely missing is where the production would be done. (masks, wafers, packaging and bonding). And some really good explanation of why it would be so cheap.
No "LOL we are in China" is not sufficient.

Which software is used to design the chips? Where do the models for the gates come from?

FYI: I am almost certain this is a scam.

I love this theory. thanks for the asymmetric information, I and other investors are able to invest into this company at such a low valuation, because people like ElectricMucus just don't believe it.

There is only one way to find out. Get them to release more information. If it is a scam as some people believe there should be no viable designs whatsoever, and if they're incompetent that should be possible to infer too. If we could find an able and willing third party that can be trusted with confidential information we might be able to convince them to release the designs, under an NDA.

Feel free to suggest people. I'm willing to pay for it myself.

[Carlton Banks]

The scam callers are also being a little unfair IMO.

friedcat has provided very extensive information, not just on the technical/manufacturing aspects of the product, but on the financial arrangements too. Although my knowledge of microchip production is limited, I know just enough to find his explanations of the issues they face (and how they're proposing to tackle them) pretty convincing. Scammers or not, he and his team clearly do know a thing or two about chip design and fabrication. Ditto the financial arrangements: I'm far from an expert, but what limited knowledge I do have leads me to believe their plan for funding the initial outlay is pretty convincing (although they're presumably not paying the foundry in BTC!)

For all we know, both ASIC companies are scams right now. But based on the evidence we do have, both organisations deserve the benefit of the doubt 

[nedbert9]

The scam callers are also being a little unfair IMO.

friedcat has provided very extensive information, not just on the technical/manufacturing aspects of the product, but on the financial arrangements too. Although my knowledge of microchip production is limited, I know just enough to find his explanations of the issues they face (and how they're proposing to tackle them) pretty convincing. Scammers or not, he and his team clearly do know a thing or two about chip design and fabrication. Ditto the financial arrangements: I'm far from an expert, but what limited knowledge I do have leads me to believe their plan for funding the initial outlay is pretty convincing (although they're presumably not paying the foundry in BTC!)

For all we know, both ASIC companies are scams right now. But based on the evidence we do have, both organisations deserve the benefit of the doubt 

I only have one response to this.

Can you do the Carlton dance?

[HorseRider]

What this thread is entirely missing is where the production would be done. (masks, wafers, packaging and bonding). And some really good explanation of why it would be so cheap.
No "LOL we are in China" is not sufficient.

Which software is used to design the chips? Where do the models for the gates come from?

FYI: I am almost certain this is a scam.

If we could find an able and willing third party that can be trusted with confidential information we might be able to convince them to release the designs, under an NDA.

Feel free to suggest people. I'm willing to pay for it myself.

This is not a viable DD request. No company will comply with this kind of request. I don't think anyone can have code of Google search engine or Coca Cola recipe under an NDA. I think friedcat has been open enough to the potential investors, especially those bulk investors. As I am already a shareholder of this company and heavily invested, I concerned the IP safety of this company myself.

[HorseRider]

his reputation is far better than BFL right now.

Like I said, I prefer the Bitfountain model overall, but that will be completely irrelevant if Bitfountain don't succeed. Under those circumstances, Block Eruptor cheerleaders will be purchasing their units from a parallel universe

Haha, this applies to BFL, too.

Before we get a real chip in hand and test it, no ASIC R&D team will be able to assure you the outcome with 100% certainty. The R&D risk of both company are equally huge.

I think both the companies are trying their best to deliver the ASIC mining rigs. It's fantastically profitable after all.  Both companies have the real world/local contacts and identity. It's not likely for both of them to scamming people's money from the crowd for 100k USD.

Given your identity is known, scam money from crowd and from a single individual is 100% different. Don't scam the crowd, scam the isolated individual, that's what happens all the time in the private industry.

This amount of money cannot even buy you a department in Beijing, Shanghai or Shenzhen. The risk for them is too much to do so, considering what they have already achieved in their social ladder climbing effort in real world.

The difference between the two is, BFL funding their venture by debt from their customer, it is not appropriate to do so IMHO without a real chip in hand. What will BFL do if the chip turns out a failure or the hash rate cannot reach what they have claimed? The same situation happened in the FPGA rigs.  I think they will delay the delivering date and accepting more pre-orders to finance their second mask. Friedcat is open and honest to the community, and finance the project with equity. There is risk of failure, but the potential return to be distribute to the investor will compensate the risk much better than BFL.

[Carlton Banks]

The scam callers are also being a little unfair IMO.

friedcat has provided very extensive information, not just on the technical/manufacturing aspects of the product, but on the financial arrangements too. Although my knowledge of microchip production is limited, I know just enough to find his explanations of the issues they face (and how they're proposing to tackle them) pretty convincing. Scammers or not, he and his team clearly do know a thing or two about chip design and fabrication. Ditto the financial arrangements: I'm far from an expert, but what limited knowledge I do have leads me to believe their plan for funding the initial outlay is pretty convincing (although they're presumably not paying the foundry in BTC!)

For all we know, both ASIC companies are scams right now. But based on the evidence we do have, both organisations deserve the benefit of the doubt 

I only have one response to this.

Can you do the Carlton dance?

Well, I'll have you know that me and my calling card are still available to perform at Meet 'n' Greets in well heeled nightclubs and supermarket openings thoughout our glorious nation  

[Carlton Banks]

I think both the companies are trying their best to deliver the ASIC mining rigs. It's fantastically profitable after all.  Both companies have the real world/local contacts and identity. It's not likely for both of them to scamming people's money from the crowd for 100k USD.

I almost 100% agree, with one proviso: not likely, but far from impossible

Given your identity is known, scam money from crowd and from a single individual is 100% different. Don't scam the crowd, scam the isolated individual, that's what happens all the time in the private industry.

Here's where we may depart absolute consensus again: I think that BFL would have a serious problem cutting out now that they and their staff are so well established within the community. It would cause irreparable reputational damage to the company and the individuals involved (look at the whole Zhou Tong/Bitcoin Consultancy issue. Intersango's drop in trading volumes seems to be connected to that, and there's no irrefutable proof of who was responsible as yet.).

The Bitfountain team don't have the same level of establishment within the Bitcoin commmunity. This is not to say that they have none at all, but you could interpret their contribution to this very cynically if you chose: currently, all they have right now is a single individual with ID verification on GLBSE, an IPO that is selling well, an iteration or two of some design/performance specifications, some product diagrams, some insight into their manufacturing issues and not insubstantial amounts of convincing talk in general. Most of that is based on this forum, and it would be a spectacular coup as a confidence trick if they were perpetrating a scam. But I disagree that you think that several months of convincing statements and interactions on these forums isn't worth a six-figure $ sum; it is (and I know that's an unflattering portrayal, I prefaced this whole thing with a cynicism disclaimer! I am, in reality, genuinely considering buying ASICMINER shares)

BFL have something tangible: products available now (admitedly not the best product out there, but a viable product nonetheless). That adds a different kind of credibility to their operation.

The difference between the two is, BFL funding their venture by debt from their customer, it is not appropriate to do so IMHO without a real chip in hand. What will BFL do if the chip turns out a failure or the hash rate cannot reach what they have claimed? The same situation happened in the FPGA rigs.  I think they will delay the delivering date and accepting more pre-orders to finance their second mask. Friedcat is open and honest to the community, and finance the project with equity. There is risk of failure, but the potential return to be distribute to the investor will compensate the risk much better than BFL.

Again, I broadly agree with this, and also would prefer it to be the truth. The trouble with BFL is that, of the few details of their ASIC product that we do have, they have not been very encouraging so far. For instance, the hashrate performance figures sound slightly too good in comparison to friedcat's figures (although BFL have quoted per device and not per chip). I can't see how a 65nm process node or a different implementation of the algorithm can really make that much difference to the hashing output. Surely each chip runs a single thread pumping out hashing solutions at whatever clock speed they can achieve with the underlying silicon? 130nm isn't so far away from 65nm, and I expect that there has been further innovation in the 130nm sphere since the desktop computing market has stopped using the process. Surely the SHA-2 algorithm can only be implemented in silicon a limited number of ways, algorithmic content is after all very specific. Perhaps some of those with some expertise could shed some light on this.

And the funding through debt to the customer model does put me off. When's a good time to buy a BFL ASIC? Now, to get a good place in the queue? (a queue which we all know is not going to be satisfied in the same order that the people formed the line) Maybe right before you expect product delivery? Immeditely after product has been demonstrably delivered? Well after product dleivery when the fuss has died down?

All options have huge downsides when you choose the date on which you buy your BFL ASIC. Not so with the way Bitfountain have arranged it.

[nedbert9]

Friedcat.

Could you offer information on the level of involvement of the foundry in validating the design?  My reason for asking is to understand if the foundry sets expectations for it's customers for failure probability given a specific design.


Thanks.

[bitfury]

What this thread is entirely missing is where the production would be done. (masks, wafers, packaging and bonding). And some really good explanation of why it would be so cheap.
No "LOL we are in China" is not sufficient.

Which software is used to design the chips? Where do the models for the gates come from?

FYI: I am almost certain this is a scam.

These factors all contribute to the inexpensive cost:
  1. 130nm node size. As the mainstream switches to 28nm, the 130nm existed for so long that even many smaller foundries could do it very well. The intense competition of manufacturing in China brings the price of everything down, including ICs. Though we chose the larger and more reliable foundry, their evaluation of the price of 130nm full-mask and MLM is still near the price in this main thread.
  2. MLM(Multi-Level-Mask). Compared to full-mask, this technology reduces the cost of mask-set to half with the exchange of increasing the margin cost by about 40%. This is a good deal for us because the margin cost of chips themselves is one of the lowest cost in our budget.
  3. Low EDA license fees and low labor cost in China.
  4. We ourselves did most of the RTL design, optimization and simulation.

The RTL is written in Verilog.
Frontend: We use VCS for simulation, Verdi for debugging, DC for synthesize.
Backend: We use ICC for P&R, Calibre for DRC/LVS check, virturso for layout merge, StarRCXT for RC extraction and PrimeTime for STA.

Formality is used to verify the netlist. We also do some simulation directly on the netlist but it is very slow compared to that on the RTL phase, so many possible cases of the state machine couldn't be covered. Formality is needed to increase the confidence of the synthesize results.

By models of the gates, I guess you mean technology libraries. They are provided by our foundry indirectly from the foundry agent.

The PLL IP module is also provided by them.

Please PM me with your e-mail address and ask for more documents and information if you feel necessary. Thanks.

I have played with mentioned softwares, shown pictures looks coherent. In my opinion success probability would be high for such approach. Tool names, etc match... I will decode what that means - VCS - is simple stuff - it's rather top-level verilog simulator. Verdi - I don't get why you need a debugger.

DC is Synopsys Design Compiler - which is usually shipped as part of ICC (top-level) - Synopsys IC Compiler.
Synopsys IC Compiler basically enables you to feed in gates and get what is on picture, and that is rather quick operation, once your RTL is good. Good sides - it would do layout for you, bad part - manual layout would dramatically for sha256 outperform automated layout, but require dramatically more time + more understanding of low-level stuff, like maintaining heights inside of chip, etc.

Calibre - is Mentor Graphics Calibre - de-facto standard for Design Rules Check (DRC) and Layout Versus Schematics (LVS) checks - DRC is basically checking of multiple design rules mentioned by fab, and LVS is verifying layout vs its schematic equivalence. Usually if you wrote (or get from fab) correct technology file for Calibre that means that your design IS MANUFACTURABLE.

Virtuoso - is a full-featured suite from Cadence - for IC design, compilation, etc... So all could be done in Virtuoso, but package at my taste looks like pain in ass...

Synopsys StarRXCT for RC extraction - RC extraction - is one of important things for design verification, as it provides exact delays caused by capacitors and resistances existing in circuit. Basically it eats layout images, and generates files for further simulations (say for example SPICE circuit can be extracted with parasitic values).

Synopsys Primetime is powerful tool to get perform timing analysis taking data from StarRXCT.

Also there can be run SPICE simulation after StarRXCT to get power consumption for the design.

I am no way affiliated with friedcat, so I can basically confirm for public plausibility of mentioned data, if they (friedcat) will decide to publish PrimeTime reports for
their design and spice simulation to get power consumption...

ALSO PLEASE NOT - THAT LAST THING IS _MANDATORY_ FOR THEM - PERFORM POWER ANALYSIS...... IT IS LIKELY THAT YOUR DESIGN WOULD NOT WORK ON MENTIONED CLOCKS
IN PRIMETIME JUST BECAUSE NOT ENOUGH POWER BYPASS WAS PLACED, AS IN THIS PART DESIGN BECOMES MUCH MORE DIFFICULT THAN PLACING SAY CPU, WHERE TOGGLE RATES DEFINITELY MUCH LOWER. IF YOU IGNORE THIS - IT MAY HAPPEN THAT YOU GET 1/2 or 1/3 OF CLOCK IN REAL DESIGN. Power Integrity could be done with Spice or maybe better specialized tools (easier)... Maybe quick simulation of single round would help you in Synopsys HSPICE or full-design simulation in Mentor MachTa (but this I don't know for sure, how well MachTa suites for power consumption analysis - I think better is work on smaller but regular portion of design using HSPICE, as full-chip sim will go for ages I believe).

MLM asic chip basically tells me that TSMC is foundry, as they widely advertised MLM technology, where you can reduce masks costs 2 times or 4 times or possible even more (it was not advertised though), when you can put several layers of chips on same reticle.

[2112]

Power Integrity could be done with Spice or maybe better specialized tools (easier)...

Have you heard of anyone using BSIM4 commercially for the last, 100% analog stages of the verification?

Maybe quick simulation of single round would help

I'm thinking minimum of probably 32 rounds: because of the multiplexer first 16 rounds are different than the remaining 48. From the non-cryptographic point of view one would want to simulate full shift register runs in both two positions of the multiplexer.

MLM asic chip basically tells me that TSMC is foundry

Maybe on the merchant, commercial basis TSMC is the only one. But for the more R&D-oriented clients Europractice offers MLM flows through the other fabs.

Anyway, this post is just an excuse to post the link for a really cool chip floorplan porn:

http://www.europractice-ic.com/docs/Annual_report_2011.pdf

[bitfury]

Power Integrity could be done with Spice or maybe better specialized tools (easier)...

Have you heard of anyone using BSIM4 commercially for the last, 100% analog stages of the verification?

This is one challenges for me - there's multiple ways to do it, but basically in flows that I saw before people
use simpler approaches. But - it would work ok for not too-power-hungry designs, while for such massive
crypto they may not work, as number of elements that are constantly switching is VERY HIGH.

Maybe quick simulation of single round would help

I'm thinking minimum of probably 32 rounds: because of the multiplexer first 16 rounds are different than the remaining 48. From the non-cryptographic point of view one would want to simulate full shift register runs in both two positions of the multiplexer.

Not exactly needed, as you can put on borders of single round construction "mock" flip-flops that will just toggle at 50% of clock speed and feed it with data.
So you can perfectly simulate power consumption.

MLM asic chip basically tells me that TSMC is foundry

Maybe on the merchant, commercial basis TSMC is the only one. But for the more R&D-oriented clients Europractice offers MLM flows through the other fabs.
Anyway, this post is just an excuse to post the link for a really cool chip floorplan porn:
http://www.europractice-ic.com/docs/Annual_report_2011.pdf

Do you mean MLM or MPW ? As MPW is multiple projects placed on single reticle, while MLM is same project but multiple layers per reticle, and MPW is usually
compatible with all fabs, but MLM requires fab to place same reticle rotated.

[2112]

This is one challenges for me - there's multiple ways to do it, but basically in flows that I saw before people
use simpler approaches. But - it would work ok for not too-power-hungry designs, while for such massive
crypto they may not work, as number of elements that are constantly switching is VERY HIGH.

This is interesting. What I've heard is that BSIM4 is the most accurate but also the slowest and least user-friendly. Pure-digital designers are happy using simpler models and more streamlined tools. It is more of a tool for the analog and mixed-signal designers. On the other hand BSIM4 is free, only the model parameters are secret and cost money.

Not exactly needed, as you can put on borders of single round construction "mock" flip-flops that will just toggle at 50% of clock speed and feed it with data.
So you can perfectly simulate power consumption.

Oh I see, a miscommunication. You meant single physical round design sorrounded by a T-type flip flops, but run for all the cycles of the whole computation.

I also meant single physical round design but also shorten the required count of cycles: 16 from the first phase and 16 from the second phase. To account for non-zero boundary conditions use standard modeling practice of topologically stitching top edge to the bottom edge and left edge to the right edge. This is cryptologically incorrect. But it is verifiable, and completely accurate as far as thermal, electric circuit and transmission-line behavior.

Do you mean MLM or MPW ?

Actually both. See page 8:

Multi Level Mask Single User Runs ... ... This technique is only available for technologies from ON Semiconductor, IHP, LFoundry and TSMC.

[bitfury]

This is one challenges for me - there's multiple ways to do it, but basically in flows that I saw before people
use simpler approaches. But - it would work ok for not too-power-hungry designs, while for such massive
crypto they may not work, as number of elements that are constantly switching is VERY HIGH.

This is interesting. What I've heard is that BSIM4 is the most accurate but also the slowest and least user-friendly. Pure-digital designers are happy using simpler models and more streamlined tools. It is more of a tool for the analog and mixed-signal designers. On the other hand BSIM4 is free, only the model parameters are secret and cost money.

Well. Maybe I am wrong, but for node sizes till 130 nm BSIM3 seems to be enough, and even for 90nm seems to be adequate. This should be enough to do +- 20% correct simulations.
For Analog / Mixed-Signal - it also depends what you want. As you may do multiple circuit tricks to actually less depend on MOSFET parameters / models and do "software" calibration stuff. Some corporations probably has BETTER models (likely say for Intel), but these won't be available to any of foreign to intel asic developer, etc. BSIM4 are more rich - but for BSIM3 I have data for example for TSMC for MANY real silicon runs extracted + also for many more foundries... This gives me ability to look for actual model parameters variation from foundry to foundry and for each tape-out. So this way for example opens potential to design foundry-independent layout.

This is what I am messing now with - I would like to get simultaneous modeling and layout flow for multiple technology node sizes. Do it once and then scale down as far as needed.

Not exactly needed, as you can put on borders of single round construction "mock" flip-flops that will just toggle at 50% of clock speed and feed it with data.
So you can perfectly simulate power consumption.

Oh I see, a miscommunication. You meant single physical round design sorrounded by a T-type flip flops, but run for all the cycles of the whole computation.

I also meant single physical round design but also shorten the required count of cycles: 16 from the first phase and 16 from the second phase. To account for non-zero boundary conditions use standard modeling practice of topologically stitching top edge to the bottom edge and left edge to the right edge. This is cryptologically incorrect. But it is verifiable, and completely accurate as far as thermal, electric circuit and transmission-line behavior.

Yep :-) Exactly :-) Do you care at power simulations that cryptography would be correct ? You don't care... You can even look at single round with round expander as huge hierarchial macrocell that do magic :-) But you need to know - how much power that magic needs and what clock it needs, and what are driving strength on boundaries and capacitances on inputs.

Do you mean MLM or MPW ?

Actually both. See page 8:

Multi Level Mask Single User Runs ... ... This technique is only available for technologies from ON Semiconductor, IHP, LFoundry and TSMC.

Nice ! Really nice ! I think that I'll go with europractice for trial tape-outs, as their access to fabs are good as well as prices are acceptable.

[2112]

BSIM4 are more rich - but for BSIM3 I have data for example for TSMC for MANY real silicon runs extracted + also for many more foundries...

Thanks for your reply. Where I wrote "BSIM4", I should've written genericly "BSIM-family". I played only with BSIM4 and only on an artificial model that was intentionally non-realistic but at the same time consistent with the solid-state physics. A classic educational toy.

Good luck with your designs.