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Author Topic: BFL ASIC is bogus  (Read 21271 times)
||bit
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July 09, 2012, 07:13:57 AM
 #21

But with that, more power usage.  I doubt a USB can support that much. It barely provides any power at all.

Clearly they're lying in their press release.  They 100% won't be able to reach their performance level indicated.

The most USB 2.0 can handle is about ~2.5 Watts.  USB 3.0 is ~5 watts.

Dedicated can go up to 10 watts but ASIC is not dedicated USB charging.  Data is also fed into the ASIC.

So if the ASIC had the same hash rate as the FPGA single it has an improvement of 16x more than the FPGA at the most. Factor in the hashing, it would have ~64x improvement.

I call BS as well.  Also there's no reason for them to be selling ASICs so cheap in the first place.  It does not make sense business wise.  They will fail and run away with pre order money since Bitcoins are their only payment option and irreversible and not easy to track and crack down in the case of fradulent transactions.

One reason to sell them cheaper might be to ensure widerspread distribution. Afterall, consolidate all that hashing into the hands of a few is suppose to be bad for bitcoin.
As for them taking only bitcoins, that is not the case. They have taken bank wires, which are traceable.

For now, I'm more interested in the power consumption question. Could ASICs do a double SHA256 hash at 3.5GH/s and be supported by only the power from a single USB port?
Are there any existing SHA256 functions performed by ASIC's that we can find specs on and determine this? This should add the weight to either it being feasability or not.

||bit

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superman3486
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July 10, 2012, 05:49:02 PM
 #22

just placed my order on a BFL SC 40GH/s , now just to wait patiently while all my 6990's cook in my basement  Cheesy
OmegaNemesis28
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July 10, 2012, 08:55:21 PM
 #23

just placed my order on a BFL SC 40GH/s , now just to wait patiently while all my 6990's cook in my basement  Cheesy

Same boat, almost :3

I'm not one for donations but if you must go ahead and I will keep you in mind. =)
http://payb.tc/omeganemesis28
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July 10, 2012, 09:42:23 PM
 #24

My point being: BFL the way it is presented to us certainly hasn't got the resources and funds to develop custom chips.

They do now.  Undecided

By custom chips I mean Full Custom ASICs, that is what they are claiming they are making. That costs about 10M USD for starters.
There might be some way to get it cheaper if you have the ties but unless whoever behind BFL is some engineering wizard he doesn't even have the means to develop it.

If you know how the process of semiconductor manufacturing actually works the notation of a BFL custom ASIC is ridiculous.
To get an idea what kind of people pulled this thing off in the past... (Ninja Style ASIC development using selfwritten software), he did it: http://en.wikipedia.org/wiki/Charles_H._Moore

They're not making a CPU just a random number generator, I'm not sure it gets any simpler than that?

It was a cunning plan to have the funny man be the money fan of the punning clan.
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July 10, 2012, 10:04:53 PM
 #25

1) Make incredible claims about your future product promise 1 to 1 trade ins on your currently sold product
2) Point all your PR tools to talking favorably about your future product and minimizing your previous failure to meet pre-release numbers
3) Take peoples $ for future orders, this combined with money not spent due to uncertainty reduces your competitors sales and thus available funds to develop their future products
4) Some profit
5) Plow some of that money into developing something that at least might, perhaps come close to your seat of the pants PR numbers
6) Huh??
7) More profit
runeks
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July 18, 2012, 03:36:53 AM
 #26

Another thing that makes the BFL announcement rather
hard to believe is the very large performance increase
they claim to be able to achieve on an ASIC as compared
to the existing FPGA solutions.

I'd have expected maybe a x3 improvement on - say - the
MH/s/Watts numbers, but the numbers they've announced
are hard to stomach.

I would love for someone really knowledgeable on this topic
(how much more efficient can a chip be made when moving
from FPGA from full custom ASIC).

Someone has actually already made a chip capable of SHA-256 on an IBM 130nm process:
http://rijndael.ece.vt.edu/sha3/chip/sha3-asic-datasheet.pdf
If I understand the paper correctly, it does 2.95 MH/s (1.51 Gbps / 256 bit / 2) (divided by two because it's double-SHA-256) while consuming 5 mW (0.005 W) running at 50 MHz. So that's about 3 GH/s at 5 W on a 130nm process.

Here's more info: http://rijndael.ece.vt.edu/sha3/sha3chip.html
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July 18, 2012, 04:37:41 AM
 #27

Another thing that makes the BFL announcement rather
hard to believe is the very large performance increase
they claim to be able to achieve on an ASIC as compared
to the existing FPGA solutions.

I'd have expected maybe a x3 improvement on - say - the
MH/s/Watts numbers, but the numbers they've announced
are hard to stomach.

I would love for someone really knowledgeable on this topic
(how much more efficient can a chip be made when moving
from FPGA from full custom ASIC).

Someone has actually already made a chip capable of SHA-256 on an IBM 130nm process:
http://rijndael.ece.vt.edu/sha3/chip/sha3-asic-datasheet.pdf
If I understand the paper correctly, it does 2.95 MH/s (1.51 Gbps / 256 bit / 2) (divided by two because it's double-SHA-256) while consuming 5 mW (0.005 W) running at 50 MHz. So that's about 3 GH/s at 5 W on a 130nm process.

Here's more info: http://rijndael.ece.vt.edu/sha3/sha3chip.html


That shows Tp at the max frequency I think, while the power is at 50MHz. If you look at mJ/Gbit, that's the same as mW/Gbps. 5.18mW given 13.76mJ/Gbit would be 0.374Gbps at 50MHz. That corresponds perfectly with 1.51Gbps@200MHz.

Looking at that paper and comparing areas, it looks like the single round of SHA2 is about 3.4% of the total die size of 5mm^2, or 0.17mm^2. Think about how many rounds of SHA2 you would need at 130nm to get 3.5GH/s.
With a full custom design you'd be able to trim off some fat because you don't need to transmit every hash out, but 3.5GH/s @~5W seems very aggressive.
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July 18, 2012, 04:44:23 AM
 #28

Another thing that makes the BFL announcement rather
hard to believe is the very large performance increase
they claim to be able to achieve on an ASIC as compared
to the existing FPGA solutions.

I'd have expected maybe a x3 improvement on - say - the
MH/s/Watts numbers, but the numbers they've announced
are hard to stomach.

I would love for someone really knowledgeable on this topic
(how much more efficient can a chip be made when moving
from FPGA from full custom ASIC).

Someone has actually already made a chip capable of SHA-256 on an IBM 130nm process:
http://rijndael.ece.vt.edu/sha3/chip/sha3-asic-datasheet.pdf
If I understand the paper correctly, it does 2.95 MH/s (1.51 Gbps / 256 bit / 2) (divided by two because it's double-SHA-256) while consuming 5 mW (0.005 W) running at 50 MHz. So that's about 3 GH/s at 5 W on a 130nm process.

Here's more info: http://rijndael.ece.vt.edu/sha3/sha3chip.html


That shows Tp at the max frequency I think, while the power is at 50MHz. If you look at mJ/Gbit, that's the same as mW/Gbps. 5.18mW given 13.76mJ/Gbit would be 0.374Gbps at 50MHz. That corresponds perfectly with 1.51Gbps@200MHz.

Looking at that paper and comparing areas, it looks like the single round of SHA2 is about 3.4% of the total die size of 5mm^2, or 0.17mm^2. Think about how many rounds of SHA2 you would need at 130nm to get 3.5GH/s.
With a full custom design you'd be able to trim off some fat because you don't need to transmit every hash out, but 3.5GH/s @~5W seems very aggressive.

1,169.893~ rounds?

If you're not excited by the idea of being an early adopter 'now', then you should come back in three or four years and either tell us "Told you it'd never work!" or join what should, by then, be a much more stable and easier-to-use system. - GA
It is being worked on by smart people. -DamienBlack
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July 18, 2012, 05:03:47 AM
 #29

Block size is actually 512 bit so it's basically 1.51 Gbps / 1024 or 1.47 MH/s
Also power goes up in a non-linear fashion as die size and clockspeed increase.

Another thing that makes the BFL announcement rather
hard to believe is the very large performance increase
they claim to be able to achieve on an ASIC as compared
to the existing FPGA solutions.

I'd have expected maybe a x3 improvement on - say - the
MH/s/Watts numbers, but the numbers they've announced
are hard to stomach.

I would love for someone really knowledgeable on this topic
(how much more efficient can a chip be made when moving
from FPGA from full custom ASIC).

Someone has actually already made a chip capable of SHA-256 on an IBM 130nm process:
http://rijndael.ece.vt.edu/sha3/chip/sha3-asic-datasheet.pdf
If I understand the paper correctly, it does 2.95 MH/s (1.51 Gbps / 256 bit / 2) (divided by two because it's double-SHA-256) while consuming 5 mW (0.005 W) running at 50 MHz. So that's about 3 GH/s at 5 W on a 130nm process.

Here's more info: http://rijndael.ece.vt.edu/sha3/sha3chip.html

runeks
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July 18, 2012, 07:28:47 AM
 #30

So if it consumes 13.76 mJ/Gbit and 3.5 GH/s equals 3584 Gbit/s (512 bits block size and two of these because of double SHA-256) then a 3.5 GH/s unit running at 50 MHz would consume 49.3W - without taking into account the added power draw from a die size about ten thousand times (0.374 Gbit/s at 50 MHz vs 3584 Gbit/s) the size of the SHA-3 chip, which would be 1700mm², or 41x41mm?

Now this is 130nm, so if we're optimistic and say they have access to a 28 nm process (is this at least somewhat realistic?), then this could be reduced to 8.8x8.8mm or 78mm². Would anyone venture a guess as to what the reduced power draw from going 120nm to 28nm would be? If it's a factor 10 and, again, we ignore the added power draw from the huge die, then that gets us down to ~5W.

Or is 28nm processes currently only reserved for companies spitting out chips in the tens of millions?
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July 18, 2012, 07:31:40 AM
 #31

28nm is not realistic at all, 130nm down to 65nm is most likely by far.
deepDown
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July 24, 2012, 04:03:58 PM
 #32

According to this:  www.xilinx.com/support/documentation/white_papers/wp298.pdf

Going from 130nm to 65 or even 45nm would give you savings at ~40-50%

Hence, the ballpark is 25-50W. No way it is going to be 5W Smiley)

if it ever materializes that is.
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July 24, 2012, 04:22:39 PM
 #33

i wonder what they're back up plan is for the "oh crap we can't meet our stated stats, and we promised..." situation...
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July 24, 2012, 05:22:45 PM
 #34

i wonder what they're back up plan is for the "oh crap we can't meet our stated stats, and we promised..." situation...

they would probably just point to the obscure statements they like to make that generalize instead of actually making any promises...

If you're not excited by the idea of being an early adopter 'now', then you should come back in three or four years and either tell us "Told you it'd never work!" or join what should, by then, be a much more stable and easier-to-use system. - GA
It is being worked on by smart people. -DamienBlack
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July 24, 2012, 05:29:08 PM
 #35

i wonder what they're back up plan is for the "oh crap we can't meet our stated stats, and we promised..." situation...

they would probably just point to the obscure statements they like to make that generalize instead of actually making any promises...
BFL would never do such a thing.

Quote from: BFL
I really dislike being drawn into these discussions but in this case it's necessary to correct you.  BF Labs has never gone on record claiming it's previous generation processors are pure ASIC.  Never.  Forum members simply came to their own conclusions based on our FAQ (which did not say it was pure ASIC, just left it ambiguous).
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July 26, 2012, 09:44:23 PM
 #36

ill keep asking myself: how could a 2.5 watt coffee warmer keep my Caffein warm? isn't that way to less power?

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August 01, 2012, 01:27:03 AM
 #37

ill keep asking myself: how could a 2.5 watt coffee warmer keep my Caffein warm? isn't that way to less power?

Depends on how insulating your coffee mug is =P

To start off, some facts:

A. Specific heat of water is 4.1813 Joules/(grams*Kelvins).
B. 2.5 watts = 2.5 Joules per second.

Now we make 2 assumptions:

1. We assume your coffee is mostly water (most are 98-99%) and that you have 250 mL (1 cup).
2. Your coffee mug is perfectly insulating.

From the volumetric density of water, we know that 250 mL of water has mass of 250g. Crunch the math and that would make it ~1050 J/K.

At 2.5 watts, it would take ~7 minutes just to raise your coffee by 1 degree assuming your coffee mug is perfect. I dont know how that thing is going to keep your coffee appreciably above room temperature if you have to account for heat loss.



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August 01, 2012, 01:40:00 AM
 #38

Wait, if it's perfectly insulating, how would it let heat through to the liquid?

Also, USB coffee warmers have been around, but can anyone that has tried one let us know whether they work?

Mining Rig Extraordinaire - the Trenton BPX6806 18-slot PCIe backplane [PICS] Dead project is dead, all hail the coming of the mighty ASIC!
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August 01, 2012, 09:38:41 AM
 #39

They work .....and kill your USB Ports :d

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August 01, 2012, 08:50:54 PM
 #40

Wait, if it's perfectly insulating, how would it let heat through to the liquid?

Also, USB coffee warmers have been around, but can anyone that has tried one let us know whether they work?

For argument sake let's just say you submerged the ASIC in your coffee =P

Doesn't work according to Amazon for lack of heating power.

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