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Author Topic: BFL ASIC is bogus  (Read 21270 times)
ElectricMucus
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July 08, 2012, 05:57:50 PM
 #1

Don't you guys remember that the Singles were claimed to contain custom hardware?

It will either turn out to be an exaggerated claim or even a scam.  
inb4 BFL fanboy shitstorm.


anyway just posting that so I can bump it next year with "I told you so."

My point being: BFL the way it is presented to us certainly hasn't got the resources and funds to develop custom chips.

First they ignore you, then they laugh at you, then they keep laughing, then they start choking on their laughter, and then they go and catch their breath. Then they start laughing even more.
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sadpandatech
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July 08, 2012, 06:02:49 PM
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http://www.youtube.com/watch?v=AKXlhpeb6wI

My point being: BFL the way it is presented to us certainly hasn't got the resources and did not have the funds to develop custom chips.

FTFY ;p

If you're not excited by the idea of being an early adopter 'now', then you should come back in three or four years and either tell us "Told you it'd never work!" or join what should, by then, be a much more stable and easier-to-use system. - GA
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July 08, 2012, 06:03:50 PM
 #3

http://www.altera.com/devices/asic/asic-index.html

ElectricMucus
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July 08, 2012, 06:07:24 PM
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That's not full custom asic, it's cell "asic" and I even doubt they even get to that level.

http://www.youtube.com/watch?v=AKXlhpeb6wI

My point being: BFL the way it is presented to us certainly hasn't got the resources and did not have the funds to develop custom chips.

FTFY ;p

fool me once.....

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July 08, 2012, 06:10:22 PM
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What will you bump with if they turn out to be accurate to the pre-released specs?
ElectricMucus
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July 08, 2012, 06:12:34 PM
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What will you bump with if they turn out to be accurate to the pre-released specs?

That I have proven the Riemann Hypothesis.

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July 08, 2012, 06:25:27 PM
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What will you bump with if they turn out to be accurate to the pre-released specs?

That I have proven the Riemann Hypothesis.

For those who don't know (including me):  http://en.wikipedia.org/wiki/Riemann_hypothesis
ElectricMucus
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July 08, 2012, 06:33:00 PM
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There I some quote about it in a book I have that in order to prove it we must first plant a tree on the moon. (Or something like it)
I know mathematicians have a strange humor.  Cheesy

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July 08, 2012, 06:39:30 PM
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You are forgetting bfl's secret sauce. Turning an altera hardcopy into a full custom asic is easy for them. You just need a bit of sandpaper and no one will be the wiser.
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July 08, 2012, 06:47:48 PM
 #10

FPGA designs cannot be easily converted to asics. Altera Hardcopy is the same device as their FPGAs with just a metal layer instead of the routing fabric.
Then there are standard cell asics which can be produced using pre-manufactured masks.
Then there are custom asics which work at the bare silicon level.


Even if they use Hardcopy my prediction would be accurate in that case, it wouldn't be a custom asic. (or even standard cell asic)
And I strongly doubt that what to would be released (if any at all) lives up to the specs.


Already made my point, just repeating the same issues.
Yes they could still claim anything they want, people will find out eventually like with the singles.

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July 08, 2012, 08:42:08 PM
 #11

My point being: BFL the way it is presented to us certainly hasn't got the resources and funds to develop custom chips.

They do now.  Undecided
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July 08, 2012, 08:46:29 PM
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My point being: BFL the way it is presented to us certainly hasn't got the resources and funds to develop custom chips.

They do now.  Undecided

By custom chips I mean Full Custom ASICs, that is what they are claiming they are making. That costs about 10M USD for starters.
There might be some way to get it cheaper if you have the ties but unless whoever behind BFL is some engineering wizard he doesn't even have the means to develop it.

If you know how the process of semiconductor manufacturing actually works the notation of a BFL custom ASIC is ridiculous.
To get an idea what kind of people pulled this thing off in the past... (Ninja Style ASIC development using selfwritten software), he did it: http://en.wikipedia.org/wiki/Charles_H._Moore

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July 08, 2012, 09:20:27 PM
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My point being: BFL the way it is presented to us certainly hasn't got the resources and funds to develop custom chips.

They do now.  Undecided

By custom chips I mean Full Custom ASICs, that is what they are claiming they are making. That costs about 10M USD for starters.
There might be some way to get it cheaper if you have the ties but unless whoever behind BFL is some engineering wizard he doesn't even have the means to develop it.

If you know how the process of semiconductor manufacturing actually works the notation of a BFL custom ASIC is ridiculous.
To get an idea what kind of people pulled this thing off in the past... (Ninja Style ASIC development using selfwritten software), he did it: http://en.wikipedia.org/wiki/Charles_H._Moore

You do make me wonder about their press release. They said they had private venture capital. Which, if your $10 million number is correct, makes it hard to think someone (or some group) would have fronted that kind of money for making bitcoin mining hardware. Unless, we do not see the size of the market well enough. What is it's size?   Anyway, other than that, at least this seems exhaggerated from the BFL press release:

Quote
“Butterfly Labs has always considered itself a serious manufacturer in the SHA-256 hardware industry and our customers are leaders in providing hashing services for some of the world’s great technological challenges,” noted Nasser G, BFL CTO. “We see the BitForce SC lineup as the natural next step in continuing to meet our customer's needs.”

What are the 'some' of the 'some of the world’s great technological challenges'?  I wouldn't say that bitcoin mining is even one of the world's great technological challenges. People were doing fine mining with GPU's (even CPU's). Since those two technologies were meeting the purpose of bitcoin mining, there was no real great challenge that needed to be met.  So, they must have done some other work outside of making Singles....  Can anyone (BFL Engineer?) help elucidate what that work was?

||bit
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July 08, 2012, 11:56:50 PM
 #14

My point being: BFL the way it is presented to us certainly hasn't got the resources and funds to develop custom chips.

They do now.  Undecided

By custom chips I mean Full Custom ASICs, that is what they are claiming they are making. That costs about 10M USD for starters.
There might be some way to get it cheaper if you have the ties but unless whoever behind BFL is some engineering wizard he doesn't even have the means to develop it.

If you know how the process of semiconductor manufacturing actually works the notation of a BFL custom ASIC is ridiculous.
To get an idea what kind of people pulled this thing off in the past... (Ninja Style ASIC development using selfwritten software), he did it: http://en.wikipedia.org/wiki/Charles_H._Moore

There have already been threads indicating that a custom ASIC on an older process could be under $1 mil USD. That being said what BFL is advertising sounds a bit too good to be true. I suppose worst case I won't mine for 2-3 months while waiting for BFL to catch up with sales/supply  Undecided

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July 08, 2012, 11:58:54 PM
 #15

My point being: BFL the way it is presented to us certainly hasn't got the resources and funds to develop custom chips.

They do now.  Undecided

By custom chips I mean Full Custom ASICs, that is what they are claiming they are making. That costs about 10M USD for starters.
There might be some way to get it cheaper if you have the ties but unless whoever behind BFL is some engineering wizard he doesn't even have the means to develop it.


Another thing that makes the BFL announcement rather
of hard to believe is the very large performance increase
they claim to be able to achieve on an ASIC as compared
to the existing FPGA solutions.

I'd have expected maybe a x3 improvement on - say - the
MH/s/Watts numbers, but the numbers they've announced
are hard to stomach.

I would love for someone really knowledgeable on this topic
(how much more efficient can a chip be made when moving
from FPGA from full custom ASIC).

I had the same initial assumption. It was based on some fast readings comparing FPGA and ASIC performance for similar tasks. The x3 or x4 numbers was what I was lead to think. However, not only has someone on this forum suggested that the performamnce would be orders of x10 to x50 increases from an FPGA to ASIC, but we have to consider the chips final fabric sizes. And there is still the manufacturers option on how many chips to incorporate in each product or submodule. But let's suppose just for discussion that the Jalapeno used just one ASIC chip to attain it's 3.5GH/s. And we know the FPGA Single is about 0.4GH/s per FPGA chip inside it. That means the ASIC would be about x9 faster (if it was just one chip), and consistent with the other forum person's view. So, it's much more than x3 or x4. But making the Jalapeno with just two or three such chips would mean the ASICS are x3 to x4.5 faster than the FPGA Single chips, and consistent with the other notions of performance improvement at hand. --- So,it seems it is possible by either presumed performance change per chip from FPGA to ASIC.

Aside from that, a question that I never followed up on from someone on the forums is about power consumption at those has rates. The Jalapeno, for exmaple is a USB device. How much power is required to generate that 3.5GH/s, and would a USB support it?

||bit
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July 09, 2012, 01:41:55 AM
 #16

Another thing that makes the BFL announcement rather
of hard to believe is the very large performance increase
they claim to be able to achieve on an ASIC as compared
to the existing FPGA solutions.

I'd have expected maybe a x3 improvement on - say - the
MH/s/Watts numbers, but the numbers they've announced
are hard to stomach.

I would love for someone really knowledgeable on this topic
(how much more efficient can a chip be made when moving
from FPGA from full custom ASIC).

This.

Just taking your FPGA-tested verilog and pushing it through the Synposys tools will usually get you an ASIC with 4x power improvement.

Working really hard to re-do the design from scratch will get you 8x.  Maybe 10x if you have really good engineers.

A 56x improvement in power consumption is just plain absurd.

The printing press heralded the end of the Dark Ages and made the Enlightenment possible, but it took another three centuries before any country managed to put freedom of the press beyond the reach of legislators.  So it may take a while before cryptocurrencies are free of the AML-NSA-KYC surveillance plague.
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July 09, 2012, 02:06:02 AM
 #17

This.

Just taking your FPGA-tested verilog and pushing it through the Synposys tools will usually get you an ASIC with 4x power improvement.

Working really hard to re-do the design from scratch will get you 8x.  Maybe 10x if you have really good engineers.

A 56x improvement in power consumption is just plain absurd.

Are you seeing anything in the PR that isn't consistent with current technological capability? As far as I can see, the PR hash rates can be accounted for with at least just using more ASIC chips per product.

||bit
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July 09, 2012, 02:21:15 AM
 #18

This.

Just taking your FPGA-tested verilog and pushing it through the Synposys tools will usually get you an ASIC with 4x power improvement.

Working really hard to re-do the design from scratch will get you 8x.  Maybe 10x if you have really good engineers.

A 56x improvement in power consumption is just plain absurd.

Are you seeing anything in the PR that isn't consistent with current technological capability? As far as I can see, the PR hash rates can be accounted for with at least just using more ASIC chips per product.

||bit

But with that, more power usage.  I doubt a USB can support that much. It barely provides any power at all.

Clearly they're lying in their press release.  They 100% won't be able to reach their performance level indicated.

The most USB 2.0 can handle is about ~2.5 Watts.  USB 3.0 is ~5 watts.

Dedicated can go up to 10 watts but ASIC is not dedicated USB charging.  Data is also fed into the ASIC.

So if the ASIC had the same hash rate as the FPGA single it has an improvement of 16x more than the FPGA at the most. Factor in the hashing, it would have ~64x improvement.

I call BS as well.  Also there's no reason for them to be selling ASICs so cheap in the first place.  It does not make sense business wise.  They will fail and run away with pre order money since Bitcoins are their only payment option and irreversible and not easy to track and crack down in the case of fradulent transactions.
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July 09, 2012, 02:30:12 AM
 #19

GDammit can we move this here: https://bitcointalk.org/index.php?board=81.0

They made that subforum for a reason.

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July 09, 2012, 03:08:04 AM
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...can we move this...

... but, isnt this the BFL forum ? <grins>

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