Well, me too. BUT there's big cons... Soldering these plugs is done by hand... and error-prone when a lot of them should be soldered... within some of them were balls of solder inside - so it was not possible to put there daughter card without pressing it too much... Then when daughter card is so small, you can only glue heatsink there and it is very RESPONSIBLE work... We did it in two person for about 3 days, and it can't be given to plant, because they can screw things... As if you put too much glue, Spartans could fry.... And we're not cooks :-)))) Fried spartan is expensive and not tasty dish )))
Then if you get it bigger it becomes 60x60 mm daughter card to put desirable-sized heatsink on it... And it wastes too much space :-( Those small heatsinks that you saw on other boards are not suitable well for such power output from Spartan.

We did it in hardware already. Yes it worth it, but not much, and in this design even less, than when we could offset whole daughter boards so they get colder air on their bottom side. It would be non-uniform then, and central chip would be hottest. You may see what we did in following pic... But I really want to remove that chip plug-and-pray technology:

Check PM.

Also - I am waiting for your release :-) And about your protection.... As this is very interesting if you can really protect that bitstream!

Because you know - what I missed actually is that I targeted at too high clock... That is possible mistake...

How long it would take to you to place a bit different round design with the way you did ?

I will tell you approx. numbers. round will be a bit bigger. ABCDEFGH round part fits into 64-72 slices depending on location.
W-round fits into 32-40 slices again depending on location.

Fitting fully expanded miner into 6 clock regions. I see feasibility there, but definitely re-starting with building tool set for that is big pain, as chip would not last that long. How long will it take for you to implement such round ? Density is very high. If your placer is good for that - then this parallel round alone might work at 240 Mhz because of round pipe-lining design, but only if you manage to place it. As "standard" placer places such design into full chip... Manually I tried only partially and then thrown this away as this fucking difficult, especially that you have to deal in tricky way around DSPs, BRAMs etc.

Then my idea - there's 2 places for rolled miners left / right bottom part and 9 rightmost, 7 mid-right, 5 mid-left, 9 left-most additional rolled round space. + 2 DSP-rounds in the leftmost part, + 2 rolled round in top part.
So 2+9+7+5+9+2 = 34 rounds can be still implemented.

Say having one parallel round - we have 1 x clock + having 0.52 more - it will be 1.52 x clock = 364 Mh/s per chip @ 240 Mhz. Higher than I can get alone with rolled design.

I'll first do precaution that nothing bad happen if they do...
And second point - there will be only one cable from one board to another board...
So one cable per board, short one like 4-inch SATA. When I saw them I loved them.

But - JTAG chain is nice to have for other applications for example.

Anyways thanks for JTAG idea!

Well. Of course it is pretty possible to change BitCoin code. Writing exactly

if (height > NNNNNN) use_SHA512 else use_SHA256, trimming block chain.

And asking people to update clients....

BitCoin were built for people, not for miners to mine coins... And not for ill-gotten miners who would try to attack network. And of course people can change things, if current things are not OK for them.... These are not for machines, because there's always SOMEONE who pays, SOMEONE who receive payment.... payment processing system is just medium... If that medium will be screwed by ASIC - then users would simply switch to another one. This could be painful switch indeed. However most will be lost by these greedy people, who just buy and hold.... But greedy always loose eventually... In things like i-mmm.com ... Or getting robbed during revolutions, etc etc :-) Don't be greed, be useful :-)

That is not plausible definition.... By logics you apply, then

http://i-mmm.com/en/index.php

is not SCAM either..... Because Sergey Mavrody pyramid pays everyone, paid out about $15 billion USD and still paying.... but often changes rules, but silll paying...

And because it pays, it is natural progression, and so one should invest there ? ;-)

Actually that scares even more than ASIC etc... That there's so many people bringing to Mavrody System cash :-)))))
Probably more than transacted in overall bitcoin history :-))) (not cap. but _transacted_, i.e. turnover)...

You can ask guy with nick 'pent' here :-)))))) He's now one of them :-))) However I thought he would NEVER join that system for example :-))))

Easily. BitCoin is small network actually. And it is small, because it was started as e-currency. "Normal" people wouldn't even understand what these hashes are about. This makes it actually interesting, because here on forum, people are smarter than average. But payment is actually application... Value is in things that you can buy with that e-currency. So if you start with thing, and then get nice e-currency for that thing - then all of your audience will use said e-currency. So when bitcoin matures and ASIC control will be in one hands - then people who would start integrating it with bittorrent world would make choice of another currency, with protected protocol depending on their need. And yes - their audience impact CAN BE MUCH BIGGER :-)

Current our position with BitCoin - we're trying it, digging into deeps What actually scares a bit - that exchanges, and people who do business with BitCoins should BUY HASHING POWER FOREMOST.... But it seems not to happen....

Yes, this can be done... But let me save how air temp. looks at output....



You mean shifting second row of boards a bit, so inlet air would be on these darker areas, right ?

11 boards in one row and 12 boards in second one ? This would help a bit I believe, but mostly volume would be hotter.

But still, isn't 2.6 kW for 4U too much ?

About plastic duct - that's bad idea, as this would add assembling difficulties = costs.

Ok. I put this board into single air channel virtual with flow setup - 293.2 K input (that's 20 degrees Celsius).

And here's thermal images I got:

Chips (Temperature of first chip in airflow - 309 K / 36 Celsius second chip - 315 K / 42 Celsius
and power supply - 326 K / 53 Celsius - however this is rude to model PSU that way... there will be much hotter parts like MOSFETs and inductors and much colder like drivers):



Board (about 308K / 35 C beneath second chip and 299K / 26 C  beneath first one ):



Air flow (cuts middle of heatsinks - air at 1 m/s overheats at about 20 C - average outlet temp.):



Now let's do some calculations to know temps inside of chip based on Spartan6 datasheets (spartan6-pack-ug385.pdf)
FG(G)484 23x23 says - 3.7 C/W junction-case and 6.3 C/W junction-board.

Let's assume Tcase = 42 Celsius Tboard = 35 Celsius and calculate Tj. Having P = 18 W.

Solve[{Tj - Pjc*3.7 == 42, Tj - Pjb*6.7 == 35, Pjb+Pjc == 18}, { Tj, Pjb, Pjc}]

Tj = 82.5 ; Pbj = 7 ; Pjc = 11

However that are not exactly true, as in model I've modeled device as piece of copper. So real temperature will be in range of about Tj = 86 degrees.

For INDUSTRIAL chip it will fit perfectly WITH 20 degrees C air input.

With 34 degrees inlet air Tj will be at absolute maximum.

So this rises questions whether we should put two such boards in serial way or not.... As IF COLD AIR SUPPLIED, we definitely can, if not - then we're screwed.

Also if we not overclock it - temperature raise would be proportionally less - to about 65 degrees C from 20 degrees in a chip. So if chips are not overclocked, then 2 such boards can be put in serial way leading to same inlet air requirements.

Also this shows that it is better to use industrial chips, although they are $4 more expensive.

Also we can increase air speed twice, and we would get only about 10 degrees temperature rise and install two boards.

So... it seems to better go to sleep and then think about this concept....

Within single 0.2 m space of 4U device one can fit 12 of such boards consuming max 1.95 kW of power @ max. clock. / max. voltage. In normal condition 1.3 kW only. But only 72 chips there.

In denser design it could be 4 kW / 2.6 kW per 4-U chassis, which seems to be OVERKILL. How to cool them down then....

You have not undermined them, as mining only small part of plan and reason is to get secure p2p currency. I assume you agree that mining is CORE security of BitCoin and BitCoin-like networks. Also mining-related business is nice way to make public contact and show that you actually have something. Possibly you could even help us, if you get this ASIC right way, it depends on you however, but your business conduct shows to me that you are more in rush for money, and pretty scared to be behind marketing-wise, that's why you put that pre-order stuff all the way etc. That's correct choice generally, but if your claims are well-backed and you really worked hard to met what you put in your ads... When not met, like your first tryout with BFL single - it damages reputation then, so many people would think that you'll do ponzi games with this buy-in offer... However ponzi schemes are even more profitable than bitcoins )) MMM-2011 proves that - about 30 billions in one year .... )))

It depends on how you will do then with that ASIC. Because what you'll end up - invested a lot of money into tech and getting chips at low cost, but you still has to return your NRE costs, and still you could benefit 51% attack for you and/or your private investors under NDA, while selling to public buyers with NRE costs included. As hashing power is basically untraceable it would be very hard to know actually what happens and that impose a security risk.

Currently it is just $5 Mio to make 51% + risks that I can buy hash power say paying 200% PPS directly for attack. Then it will be $XX Mio to make 51% + risk of massive hash power buy + your company having ASIC NDA that can make chip for pennies, but still has return NRE costs and selling it at "market" price par-to-par with FPGA prices that board vendors could get :-) But for being safe, truly - either algorithm should be changed, but not the way like Scrypt, OR ASIC should be widely available and with current way fabs work we smash into the WALL :-)

Ahh. I forgot also about another security risk - http://www.dwavesys.com/en/dw_homepage.html ... Commercial, not military indeed :-) But this CAN BE MITIGATED :-) Although different crypto-system should be deployed.... With FPGAs - we can reprogram them, while with ASICs... hmmm...

Then what ? We need p2p currency for a project that abandoned but still actual long time ago.... This is the thing that Satoshi invented but we couldn't... We were not that smart, skillful and lucky... Bad that there's no contact with him... But maybe, when real wars with Goliath begins he reappear, there's not much skillful people :-)

What we do then in need of p2p currency but high security risks, how you think ? ;-)


Yes, but you have put 20 W / 1 Gh/s unit when started taking pre-orders and then it was 80 W / 800 Mh/s unit. That's significant difference. That's not we did... We haven't took a penny from anyone here :-)

Same could happen with buy-back offer.... And with long-term usage of your devices etc...


Well. It is just about claim - not structured asic, but full custom asic, etc etc :-)


That hostility is the result of your business behavior. Already mentioned several times in this message.

Why would we start own device and not just contact you and ask for one of yours ? We've thought first, but
when looked on small-sized item with 20W without cooling and PREORDER button we thought that it's pure SCAM
and one who drawn that didn't know that it would be extremely hot... Why would we expect anything DIFFERENT then ?

Now we're inside and probe exactly how things are with mining, etc... As it is difficult to analyze true security of network other way and give correct predictions.


Kind regards,
BitFury Group

The proposed board. Mechanical drawing. Board size is 190 (width) x 160 height. Total height is about 32 mm (counting board width, chip width, and heatsink height of 28 mm).

1. Thanks to guys who showed me http://www.raspberrypi.org/ controller
    That controller has nice GPIO outputs, that could drive FPGA legs. And that controller can drive multiple boards at once.
    So no microcontroller per-board required.

    Just some GPIO pins would be used for SATA.

    It costs only $25 per item.... Which is nice, so when connected to multiple boards, cost of controller would be little.

2. Thanks to DiabloD3 for SATA cables idea, so when decided over JTAG vs non-JTAG I decided to put them all!
    SATA1 is input SATA2 is output to next board of following signals:

PIN1 - SCK
PIN2 - MOSI
PIN3 - MISO
PIN4 - GROUND
PIN5 - RESET
PIN6 - PROGDATA
PIN7 - PROGSCK

    SPI interface to talk with bitstream and another SPI to program bitstream plus generic RESET.

    And another SATA interface, again SATA3 input, SATA4 output:

PIN1 - TMS
PIN2 - TCK
PIN3 - TDI
PIN4 - GROUND
PIN5 - UNUSED
PIN6 - RST
PIN7 - TDO

    On board design will contain buffers and resistors connected in a way, that connecting these cables in wrong direction won't cause problems.

3. PSU is TPS40090 based 100 Amp power supply, but used at lower amps to get performance better, in overclocked
    condition performance at about 90% expected, in normal conditions about 92-94%. Amps delivered are quire high.
   Also PSU input would be in 10 - 15 V range, so it can be connected to automotive power supplies / lead acid backup /
   wind energy storage batteries directly if someone would like to do it.

4. Connectivity of 12 V is via MOLEX socket (4-pin) and also can be connected via bolt connection to copper bus / bar,
    which could be used to mount boards as well. (This 12 V connection is specifically for Greg). However in our chassis
    we may put separate cables with molex connectors and add fuses on them. If will be requested - we may add fuse on
    board by adding special PCB layout, that will burn if there will go about 20-30 amps current suddenly.

5. Board has connectors on TOP to not distract airflow, and also they would sit tightly there, when pressed by chassis top.

6. There will be 3 jumpers around PSU that would select voltage level - 1.15 V to 1.5 V in 0.05 V steps. We will set it up @ 1.3 V which is safe by datasheet. That way performance could be improved up to 280-290 Mhz clock depending on chip when voltage rised to 1.5 V. TSP40090 actually useful for that.

7. Every board would have 6 jumpers to select board identifier, that can be later used by software.

8. Communicating with board will be done using 32-bit SPI. Basically you first supply 32-bit command and then either read or write 32-bit word of data. 32-bit command would contain address (6-bit board number 3-bit chip number), command type (read or write 1-bit) and register number (5-bit) totalling 15 bits AND some framesync/error check information for quick bus resetting etc.

This communication can be made practically with every GPIO software, and even with LPT-port via resistors, at any clock rates, which will not produce significant error rates. So board will be as cheap as possible then. WITHOUT any RS-485 or USB interfaces. And without any FLASH chips on it.



In next message I'll write about temperature simulations... For maximum overclocked mode - 18W per chip on 1.5 V / 18W on power supply dissipation and 1 m/s airflow...

Then I'll go drawing draft for 4-U device.

We're scared full custom ASIC is great!!!!! You would invest probably more than whole BTC worth then if you would go with say 45-nm!!!! You are serious player  I think this is the time, when security of SHA256 for block-chain generation should be .... IMPROVED   But let's go step by step  First deliver mini-rigs with nice performance and cost, then ASIC, then do buy-in, and then everything would be secure, under NDA of course Or ? Will you start again taking money for future product with "variable" performance ?   

Well. I am pushing now hard to make LX150 at price near/below BFL. Talking to many people found that Rack design we built for ourselves and our investors in not that people want. So we started 4U-box design initiative. Although single-boards orders may be supported as well. And meanwhile discussing with FPGA-vendors about prices. I suppose that first batch for 4U devices will be around 500 chips, not less, if good price needed.

https://bitcointalk.org/index.php?topic=83332.0

I'll soon (hopefully today) post mechanical drawings of board there, airflow simulation, protocol proposal, etc. Meanwhile soon I'll meet with Altera guys and discuss future of their chips vs LX150... But that fastest LX150 bitstream actually makes hope that we'll get good prices for Altera for more or less baseline unrolled bitstream like I used in sims here priced competitively... Then there will be quite long iteration to improve Altera's bitstream, which could take about same 6 month... etc... Opensource releases will lag of course closed-source production, as I suppose that crowdfunding like offered here

https://bitcointalk.org/index.php?topic=83332.msg918125#msg918125

would not bring money necessary to make all these things work.

So all of these gives me clue that today we'll get "competitive" price at about $0.60 per Mh/s, at the end of year about $0.45 per Mh/s, in mid of 2013 at about $0.30 per Mh/s etc, at about end of 2013 at about $0.15 per Mh/s, and then it finally would land on Moore's law with ASIC things but like cell-asic 45-nm with some custom cells indeed, decreasing with less speed. But - to make these things to happen, overall mining market should grow (i.e. difficulty AND exchange rate of bitcoin), so it would be interesting to throw more resources to developing these things. So I feel with FPGAs in much safer region.

https://bitcointalk.org/index.php?topic=76351.msg925049#msg925049

That's for ngzhang and all folks - I've run some comparison of FPGA vs ASIC Hardcopy...
Artix7 allows tricks like LX150 unlike Cyclone V though. So by following that thread,
you can understand why claims about 28nm being obsolete are questionable.

Not exactly. It is just extremely complex work to get LX150 to make it nice. And other thing is extremely complex to deal with FPGA vendors when have unstable demand. Building several racks already enables to make better deals by just showing them how this thing may look like. Because these single-board sales does not impress much.


Obviously. But Altera Hardcopy-based design would still have gap against same size chip, but with custom-designed ASIC. I've even mentioned in one topic how this should be done.



I just took one of my versions optimized for altera devices (unrolled prototype, and optimizations are made this time for size, not for clock as with LX150) and got following performance (tried to lay it on chip):

Device EP4SE230...C3: fmax about 253 Mhz, number of unrolled miners - 4 - That's about 1 Gh/s (not tried in H/W)
Device EP4SE530...C3: fmax about 249 Mhz, number of unrolled miners - 8 - That's about 2 Gh/s per chip.
Device 5CGXB... C7: fmax about 163 Mhz, number of unrolled miners - 2 - That's about 326 Mh/s per chip.

Quartus optimizations does not matter much here however, as most reward is in logics layout within design. Still NEITHER OF THAT DESIGN VERIFIED IN HARDWARE. So one just can pray, that same performance due to extreme toggle rates will be in hardware. I expect that there will be clock degradation in Stratix IV chips and no degradation for Cyclone V because of consumed power. What's nice about CycloneV compared to LX150 for example is more than twice less power consumption, however performance is near the same. Design like with LX150 is unlikely to get there due to routing limitations as there's more wires for routing unrolled round, while less resources to enter LAB, and so it is unlikely to get dense packing there as could be done with LX150.

First tryout:

Device: HC4E25FF484 ; Slow 85C model - 321.34 Mhz clock;
Synthesis tool says: 208'723 H-Cells / 98'873 block memory bits
Fitter tool says: 371'641 H-Cells / 98'873 block memory bits.
So what's your quote was ? out of synthesis tool or of fitter tool ?

Then I've started counting by M9K blocks - and found that there's not enough of them - as only about 5 miners can be put into HC4E25FF484 that way. And I expect about 10 miners into 9M H-Cell chip. That's not good indeed, as M9K/H-cell balance is completely different!

Second tryout (making it less consuming M9Ks by switching hard-coded M9K altsyncram to altshift_taps):

Device: HC4E25FF484 ; Slow 85C model - 340 Mhz (but 362 Mhz if not counting m9k limits);
Synthesis tool say: 212'327 H-Cells / 27'778 block memory bits.
Fitter tool says: 382'488 H-Cells / 27'778 block memory bits.

Please note, that clock increased, this is due to improved density... With such thing I would say it would fit about
10 of such things into 5M chip and about 18 into 9M chip to stay safe with the clock and not packing it too dense.

Third tryout (removing M9K blocks completely, as it seems that it would be more dense with everything implemented in FF pairs).

Device: HC4E25FF484 ; Slow 85C model - 367 Mhz ;
Synthesis tool say: 277'929 H-Cells / 0 block memory bits;
Fitter tool says: 516'059 H-Cells / 0 block memory bits;

Looking at floor plan gives me clue that about 8 of these miners would fit into 5M chips and 14 into 9M chip without making tough problems. As you see, I am _lowering_ numbers significantly... Because if I even manage to squeeze things so hard, it could end up with clocks not like in tools, but like 200-220 Mhz...

So it will be likely about 6 Gh/s per single chip HC4E25FF484 with decent design, not 8 Gh/s. However that's without specific hardcopy-related optimizations... If spending additional 2-3 month on it - mine design could be improved to say 7-8 Gh/s potential, but not so much like on spartan6 indeed. For ztex or fpgaminer I suppose it would be less at about 4-5 Gh/s per such chip.

Then - I rise following question - if we say sign contract to buy Artix7 chips in quantities compared to ASIC development and production costs - would prices be SIGNIFICANTLY less ? Say like $30 per chip, while getting of about 0.5-0.6 Gh/s ? Then if so - what's the point to go into ASIC ? This is even less than planned for ASIC...

With ASIC however that would be even easier to do, as this would proof to Xilinx that if someone invested $2M into ASIC building, then definitely there exists market and they would lower their FPGA prices to be competitive.... So from hardware design point of view ASIC blow offs, but looking from other - financial point of view - sASIC does not offers much benefits compared to FPGA internal prices to their vendors - so this game could end with epic failure. However this would be still nice investment and result for community overall, as Mh/s would be lower, but I would rather choose gradually slow step-by-step evolution as there's no need to hurry.

Do you really think that cost of silicon differs so much ? Actually what makes costs here is the IP, design, etc... Stratix IV and Cyclone V costs internal to Altera to build would have costs compared to their silicon die area... But they sell it at different prices because NRE costs very different for these chips, and they want to recover their R&D costs.


I would say that all of that extremely preliminary.... And I even doubt that until first payment to Altera goes, you would even know how tight chip could be filled... And even then with such toggle rates and sASIC (I suppose they design chip having 12.5-20% toggle rates in mind) there could be problems with logics powering, if you compact it too dense.

That's FPGA-based solution...

https://bitcointalk.org/index.php?topic=82941.0

Possibly we started new way - not mining rig, but a 42U mining rack :-)))))) A few racks only however... But there will be much more, not racks however, but 4-U devices producing gigahashes.

https://bitcointalk.org/index.php?topic=83332.0

Soon I'll do some modelling about that future device, that can be used @ home and @ DC. And very soon production will start. Looking for ppl interested in first 500 chips (actually possible minus 220 chips because I have already some requests). And even more interested in those who will help us to sell. And also, right now you can take part in this development. However - very very soon - on 1-5 June it will be deadline for updates. So if you want some features, better to write about them right now, or it will be too late for first units. As every PCB/chassis redesign costs money, it is unlikely that we will be doing this every time.

Dunno what to say about ASICs vs FPGA... About ASICs - I've told in other topics, that doing really nice ASIC
would be difficult... And that such difficulty is well beyond to best our bitstream up to date for Spartan6 chips.

If someone would do Altera Hardcopy for example, that could be difficult to match against 28-nm upcoming chips. Well,
of course if you count in price of resulting chips also NRE costs invested... If counting just chip prices without NRE costs - then ASICs would look nice... But that's like counting video boards installed, not counting motherboards and electricity consumed in mining... So while these ASIC vs FPGA debate go - we do what we do, and it is definitely better than debating... If at moment of FPGA release, there will be massive FPGA installations and like +3 Th/s with Spartans, and then +7 - 12 Th/s on 28-nm FPGAs potential in the future, that would be nice countermeasure against ASIC deployment.

Going at first to lower $ / Mh/s rate for FPGA to levels of $0.60 without VAT. However if someone would manage implementing ASIC like implemented in ATI/AMD chips for example - that would be killer for FPGA, but that's unlikely for next year for sure, as there very few FPGA developers started to get here, and zero elite ASIC developers.

What's good with ASIC/FPGA solution - is that you can put several racks in your house basement and get significant hash rates. Also you can produce and use heat in useful manner. Currently with these two racks you can do that:

orion .bitcoin $ egrep 'CBlock|height' debug.log | grep CBlock -A 1
CBlock(hash=00000000000004e4e1ec, ver=1, hashPrevBlock=00000000000002544a75, hashMerkleRoot=70af1890ee, nTime=1337926615, nBits=1a0a8b5f, nNonce=3066984747, vtx=299)
SetBestChain: new best=00000000000004e4e1ec  height=181502  work=333956803896197172810
--
CBlock(hash=00000000000005a4b5c3, ver=1, hashPrevBlock=00000000000000932258, hashMerkleRoot=9060425c62, nTime=1337938808, nBits=1a0a8b5f, nNonce=604793349, vtx=487)
SetBestChain: new best=00000000000005a4b5c3  height=181519  work=334072977122612445984
--
CBlock(hash=000000000000075be0b9, ver=1, hashPrevBlock=000000000000053744b0, hashMerkleRoot=31f4bf86c4, nTime=1337963994, nBits=1a0a8b5f, nNonce=3201488052, vtx=414)
SetBestChain: new best=000000000000075be0b9  height=181545  work=334250653821835804956

That's also answers questions - why we tried moving hashing power to deepbit. As you see we have found third block.... but on block chain there's different block... and that is annoying :-)))) We'll first investigate and then apply patch to this issue :-))))

But first fixing internet connection to level, when there will be constant hash output rate without any glitches, and then investigate what happens on the level of network protocol with modified bitcoind and a few monitoring nodes.

Hopefully I've answered question in proper topic.

PS. And also - this is easily could be verified - first deepbit could review shares and find that they are a bit different from regular miners - as there's only specific subset of work processed because of 82/128 core design (each core processes parts of nonces). Also you could see that bitfury.org really has working hashing power, and not some kind of talks. Actually shares and method of getting work could be easily identified by freq. analysis of some bits of nonce.

в смысле чтобы по одной плате на человека приходило ?

а какой лимит стоимости для одного человека не облагаемый ? сервер так скорее всего не проедет...

плюс кто отвечает за то, что граница стопорнет кому-то платочку ? и платочка не доедет ?

т.е. если вы забираете скажем в Гонк-Конге партию, а потом рассылаете самостоятельно - можно организовать со временем... ну или мы организовать можем, с какой-то наценкой на работу специализированного человека по таким заказам... сколько заказов-то будет ?

но качество такой работы скорее будет на уровне "как есть", правда и цену можно поставить тоже пониже за плату в таком виде, с риском того, что она до покупателя и не дойдет вообще.

Not exactly. I mentioned case when you do adding in 32 clocks.... One bit at one clock edge. So one D-trigger holds output, and other D-trigger holds carry, which fed back to adder on next clock.

So you get ONE wire instead of 32 wires for round expander fully unrolled. Still design is pipelined.

But you need really long and compact shift registers without access to internal bits of course. These are required to do rotation operations (basically by delaying for 32 clocks all variables in calculation, but doing different delays for RORs). And then really long delays for W round (that would be 224-bit delay line and 256-bit delay line).

I've tried to experiment this with BRAMs - it is nice - when you have 32 rounds of round expander around single BRAM :-)
but actually static RAM is nowhere near efficiency and density of such shift registers implemented in silicon.

As this register would work only in dynamics, basically you need only capacitor to hold bit and circuit to charge next capacitor on clock pulse. It will not work at slow clocks then of course. And as far as I know it is extremely hard to implement such circuit in silicon (basically because I have spoken not with elite ASIC developers indeed).

If that approach would save 3-4 times transistor count compared to serie of flip-flops, the design then would shine :-)

Well, possibly we can meet and discuss it. Because it is unlikely that it would be EXACTLY the same, very unlikely. As the design I made - I know that it is not absolutely the best one that could be done, and there's room for improvement. However efforts required are not justified, especially with epic failure about powering that logics inside. Also all path of design evolution is even more interesting than design itself, as I have for example interesting approach for parallel design with W-expander around DSP48. I've aimed about 350-370 Mhz clock originally - so this IS DEFINITELY point of failure, and if I would relax clock and target it at about 300 Mhz - it _could_ be implemented more efficiently. Also there's interesting possibility to mix parallel computation and serial rolled computation in 1:3 etc. (that's of what I had before).


Yes, making BitCoin ASIC available from different suppliers is nice idea. But someone has to invest funds into it. And it seems that community has no interest to invest say 10% of owned BTC to finish this moment up... About "elite research group" - that's exactly what I mentioned about.... All you can get say for $500k to produce ASIC would be unlikely "elite"... I suppose that AMD, Nvidia, Intel, military consume resources of elite research groups at much higher rates, than single investor would afford. Then if when elite group would do ASIC at high costs concentrate efforts on backwards 90-nm ? It should be AT LEAST 45-nm then... As this would rock... And true ASIC of course, not things like structured asic or fpga hardcopies.

ABOUT ASIC - One interesting thing that I have researched - single-bit design. I.e. instead of carry chains you use D-flip flop for carry and D-flip flop for result. Then it would require 32 times less wires for W-expander. Allows constant-optimization. This would be smallest CORE, but with one IF - IF you are capable to design long digital delay lines (i.e. like SRL16 in spartan) within chip. I know that it is pretty doable. But nobody I contacted can work at that level, and basically it is unlikely what you will find in cell library from TSMC for example. This carefully designed thing can beat everything and rise calculations speed at silicon maximum. I doubt however that there's many _developers_ who would even understand what I wrote about here and zero who can do that not in theory but with more or less guaranteed result in hardware.


well. it is pretty doable (about 51% for bitcoins) following way (also point for FPGA at current period vs ASIC) -
 I have request for video transcoding at large scale - people inquiry whether I can beat with cost of these chips installations of servers/gpus for that. Typical need - tranform video file from formats:

(S)VCD (Super Video CD);
DVD, including encrypted DVD;
MPEG-1/2 (ES/PS/PES/VOB);
AVI file format;
MOV/MP4 format; Ogg/OGM files; Matroska.

codecs:

MPEG-1 (VCD) and MPEG-2 (SVCD/DVD/DVB) video;
MPEG-4 ASP including DivX and Xvid;
MPEG-4 AVC aka H.264;
DV video;
MJPEG, AVID, VCR2, ASV2;
FLI/FLC.

into:

MP4 H264 AAC

at bitrates:

'1080p' 4M (720p < height <= 1080p)
'720p' 2M (480p < height <= 720p)
'480p' 1M (height = 480p)
'480p-' 512k (360p < height < 480p)
'360p'  512k (height = 360p)
'360p-' 256k (240p < height < 360p)
'240p'  164k (height <= 240p)

that's for flash tube web sites...

So if farm can do this work - and process multiple petabytes of videos more efficiently than on own server hardware or like purchased work on clouds - then they will be definitely willing to invest more, as this is not only bitcoin-targetted then, and when ASIC comes in play - this farm would still be useful for other computations.

The problem is - that supporting all of that codes is ton of work. And also designing more or less universal board for computations is tough part as well. But it would open more financing for FPGAs - say on demand it transcode videos, and then in idle calculates bitcoin. If later it could be possible to run rendering there - it would be even more beneficial, however that's yet higher ton of work, and it is quite difficult to estimate feasibility of FPGA vs GPU for rendering.

If this is doable - such farm could be nice step into ASIC development for bitcoin world, still investments into it would be secured well and much less risky.

This is interesting. If you manage to get it working at clocks that TRCE says - it would be interesting indeed, so we could improve. Because I doubt that our designs could be similar, maybe we can produce even higher speeds by combining techniques used. If you have right equipment around - check power. I expect that you have higher speed of prototype PCB delivery, so maybe several designs should be tried to actually deliver necessary power into spartan. For me such experiments are quite difficult, as I have typically to wait 3 weeks before getting PCB of required quality to solder there Spartan.


That's exactly is the point.... But when I started talking about ASICs - with guarantees developers given me quotes for 90nm in range of 500 Mhz .. 1 Ghz ...  That they will re-do design, re-order wafers in case of failure. And when I was talking about pushing limits to what Intel does with their chips - many said - sorry - we do not have right experience to do that. So the same thing stopped me going with ASIC. And also having current BitCoin size - seems almost nobody interested to seriously throw money in into such risky perspective.

Then - exactly - costs only 5M$ to get 51% of majority. For system with 40M$ market cap it is ok, and way better than banks. But if someone would like to invest say 1M$ to build big project using BitCoin - he face with the question - okay, my project will grow, and then will grow BitCoin cap. and then making 51% attack would be more feasible. Imagine if product, say like better, functional system like skype would emerge within BitCoin ... and its market cap goes to $2 billions...  would Microsoft pay that $5M to disrupt it ?

BitCoin is actually enabler for very interesting AND NEW p2p technology, that internet lacked from its beginning - solution of problem that currently solved by advertising online, that can be built and blow off many very big projects, doing them obsolete . But once BitCoin would start doing that - it would face real battle ..... As this basically would mean making whole business model of TOP-10 internet companies obsolete... That is actually much worse than single Bank of America... So that BF-110 was also estimation - how well BitCoin is prepared for that battle... Unfortunately not very well, a lot of work ahead. Most pity that it seems that these owners of $40M worth of Bitcoins don't really get how this thing important is, and why things like Scrypt-modified versions etc would not help much here, as BitCoin blockchain protection should lie tightly on Moore's law curve.