BFL SC Die Guestimation/Speculation

[makomk]

Standard-cell ASICs and synthesis-flow ASICs are not considered full-custom chips.

The phrase "fully custom" is a BFL-ism that sounds a lot like "truthiness"  In fact the third google hit for "fully custom asic" on the entire interweb is BFL which ought to be a hint that it is a contortion of the usual industry terminology...

I've pointed this out to Inaba too. He also claimed that the fact bASIC had said they were using cell-based ASICs meant that they were using structured ASICs and wouldn't be able to compete with BFL's chips on power efficiency. I'm fairly sure that's wrong?

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[Bogart]

Some general information on ASIC design and production:

http://en.wikipedia.org/wiki/Application-specific_integrated_circuit

http://electronics.stackexchange.com/questions/7042/how-much-does-it-cost-to-have-a-custom-asic-made

[SLok]

http://www.youtube.com/watch?v=bT-smMzg54k&feature=relmfu

at 0.48  "full-custom asics, etc

 

By the way, BFL doesn't use the phrase "full custom" to mean the same thing it means in the industry.

We don't?  Please elaborate. (I'm serious, I'm not being snarky.  If we/I am using it incorrectly, then I would like to use the proper term.)

Standard-cell ASICs and synthesis-flow ASICs are not considered full-custom chips.

The phrase "fully custom" is a BFL-ism that sounds a lot like "truthiness"  In fact the third google hit for "fully custom asic" on the entire interweb is BFL which ought to be a hint that it is a contortion of the usual industry terminology...

[sadpandatech]

If Altera HardCopy is used it will be on 28nm, with a maximum of 11.5M gates, or a maximum hash rate of 12.35 GH/s at 1 GHz, but these run at 400-700 MHz typically.

If this really is the case, the power usage will not be much less than the corresponding ASIC.  Altera themselves state, "Average of 50% performance improvement over corresponding FPGA, average of 40% less power consumption compared to corresponding FPGA."  Thus, from a hash/s/w standpoint, the ASIC would be about 200% greater than the corresponding FPGA.  A by-hand design like that of CAST's ASIC would be the only ASIC able to really deliver the kind of power consumption BFL has been hinting at.

That is their older, outdated hardcopy process.

see the new hardcopy info starting here;
http://www.altera.com/devices/asic/asic-index.html

[mem]

By the way, BFL doesn't use the phrase "full custom" to mean the same thing it means in the industry.

We don't?  Please elaborate. (I'm serious, I'm not being snarky.  If we/I am using it incorrectly, then I would like to use the proper term.)

"Full of Shit" is the term I use to describe you and your companies claims frequently Inaba, feel free to borrow it.

Honestly as you work for and defend a predatory con artist who scammed senior citizens out of a some totaling over 26 Million USD I think shit is the nicest thing you could be full of.

[Bogart]

http://www.youtube.com/watch?v=bT-smMzg54k&feature=relmfu

at 0.48  "full-custom asics, etc

Full Custom huh.

Reading some on the different ASIC types here:
http://electronics.stackexchange.com/questions/7042/how-much-does-it-cost-to-have-a-custom-asic-made

They say that the pros of a Full Custom ASIC are the same as with a standard-cell ASIC, but more so.  A Full Custom can deliver even better performance, smaller die size, reduced power consumption, [presumably] lower cost per unit to manufacture, etc.

The cons are also the same as a standard-cell ASIC, but more so.  Design cost and effort required is even higher, and "Odds of screwing something up is much higher".

If BFL is indeed going for a Full Custom design before anyone has even done a [simpler] standard-cell design, I would call this a "shoot the moon" approach.

http://en.wikipedia.org/wiki/Hearts#Shooting_the_moon

[MrTeal]

With a standard cell ASIC, default structures are used. Say you want to place an inverter, it might end up looking something like this (in Cadence Virtuoso)



If you want to easily chain together different structures, it works out very nicely. It doesn't mean it's always the most efficient way to lay out a design though. With a full custom ASIC, once you have your schematic you can move away from standard cells and lay out the design in the most efficient way for both size and speed by moving around the location of the transistors and metal layers.

For SHA this would be much less expensive than a comparable sized chip, since you really only have to optimize one hashing engine. All the rest can basically be repeats of your single design.

[maxxoccupancy]

I've also seen something like 654,000 logic gates for a full SHA256 pipeline, which is, of course, much faster than one that has just the 13.5K gates functional unit taking 65 cycles.