With a standard cell ASIC, default structures are used. Say you want to place an inverter, it might end up looking something like this (in Cadence Virtuoso)
If you want to easily chain together different structures, it works out very nicely. It doesn't mean it's always the most efficient way to lay out a design though. With a full custom ASIC, once you have your schematic you can move away from standard cells and lay out the design in the most efficient way for both size and speed by moving around the location of the transistors and metal layers.
For SHA this would be much less expensive than a comparable sized chip, since you really only have to optimize one hashing engine. All the rest can basically be repeats of your single design.