And some more delays in BFL shipment plans / no shipment before 14th Jan 2013

[Bogart]

After talking with our liaison tonight and still having not received a final confirmation date, we were as tired of this as everyone else is, so we continued to push for a date and they gave us 30 days from today.  That's my update.

Sad but true... Next year... maybe

and that's when the chips arrive, not even assembled yet.

or tested.

[Phinnaeus Gage]

Thanks for blowing my Christmas Carol rev 2.1 plot buddy!

To make it up to you, have at It's a Wonderful Life, but check your pockets first making sure Zuzu's petals are still there before preceding.

[creativex]

lol

[Starlightbreaker]

After talking with our liaison tonight and still having not received a final confirmation date, we were as tired of this as everyone else is, so we continued to push for a date and they gave us 30 days from today.  That's my update.

Sad but true... Next year... maybe

and that's when the chips arrive, not even assembled yet.

or tested.

i'm too lazy to dig my old posts.

but i'll just put these here for those preordered from BFL.


"fucking told you so"
and
"called it"

lol


as per inaba said, they are indeed has more experience and the industry leading expert in DELAYS.

[Syke]

You are referring to a past event, not a policy that extends into the future. "We always have." is strictly a past event. What about the future? Will every refund request be honored in the future?

So let me get this straight... you want me to ... wait for it ... predict the future.

For someone who won't "predict the future" regarding his own company's policy, you sure do love to predict the future of your competitors:

That said, after reviewing the new information coming out of the bASIC camp and the Avalon camp, I'm pretty convinced we won't see a shipping product on their current timelines either

Congrats on yet another delay. Stop with the CYA and make the refund policy official and put it on the website. You owe it to your "customers".

[Mapuo]

We need some partially refund for every pre-order, or free Jalapeno, or free(DHL express international) shipping($88 refund), for all these delays.

[greyhawk]

Merry Christmas, everyone. 

[ab8989]

https://forums.butterflylabs.com/bfl-forum-miscellaneous/519-10-dec-2012-bfl-asic-update.html

I smell a very thick layer of decoration on the story. For example I cannot imagine such level of unprofessionalism involved in the communications here. The ASIC manufacturer is a billion dollar business and has its customers a healthy mix of other billion dollar industry behemoths which have managers handling their major projects that all would 100% totally flip out if their component supplier (non-)communicates to them as customers like that.

But to cut to the chase the bottom line I read here is that you do not have the mask set done and you don't have clear understanding of the process that needs gone through to get the maskset done.

The maskset is the one huge expenditure that the ASIC foundry would be hesitant to spend unnecessarily. After the maskset is done, there is no reason not to let the train run its full course until the endstation. The costs involved are relatively minor compared to the huge upside if you happen to find yet another fault which you must correct for the next iteration.

You have clearly designed the chip too aggressively breaking some design rules that have now caused some speedbumps on the road. Professionals should have understood the design rules that need to be followed so that the speedbumps are either avoided or taken with full intent of doing so. If they come as a surprise you have at least failed to ask the right questions earlier.
Well these things you learn and next project you can do better.

What is the number one reason, why most companies are really afraid going to full-custom? I mean full-full-custom and not just standard-cell which sometimes somebody is also calling full-custom but clearly you are not doing so.
Well the reason is that ASIC projects have huge risks involved and going full custom further increases the risks exponentially. No matter where and what the risks are when they are finally realized, they still come back to the underlying rootcause of taking on the exponential risks when deciding to go full-custom. In your case I don't quite understand what was the upside gained from full-custom other than it has so expensive ring to it so it could win some preorders with that ring.

[bitcoindaddy]

Merry Christmas, everyone. 

The Jalapeno I ordered is a christmas gift for my son. He's going to have a very sad christmas this year.

[greyhawk]

Merry Christmas, everyone. 

The Jalapeno I ordered is a christmas gift for my son. He's going to have a very sad christmas this year.

The WiiU is out. Please save Christmas.

[bce]

We need some partially refund for every pre-order, or free Jalapeno, or free(DHL express international) shipping($88 refund), for all these delays.

This would be a smart move - to do something to at least try to make things right.

[creativex]

We need some partially refund for every pre-order, or free Jalapeno, or free(DHL express international) shipping($88 refund), for all these delays.

This would be a smart move - to do something to at least try to make things right.

...unless it bankrupts this tiny company, in which case it'd be better to either get a refund as early as possible or just sit tight and hope they get their ducks in a row eventually.

[wdBTCtrader]

I agree that they could do a better job with the updates, but this isn't news.  If a little common sense is applied it could have easily been assumed mid January.  I predicted this before any announcement made by BFL, and BFL quickly responded that mid January was a fair assessment. 

https://forums.butterflylabs.com/bfl-forum-miscellaneous/511-earliest-date-expect-delivery-january-25th.html

[creativex]

Shall I dig up the posts where I said the very same thing to BFL's COO and he suggested BFL could still ship in December of 2012? ...he also suggested, I was a stupid, idiotic liar, and a waste of human flesh, but that's not really relevant.

How about the email from a BFL CS rep posted to bitcointalk suggesting that BFL expects to ship late December or early January?

They're liars bud, they're not nearly ready to ship finished ASIC products and they know it.

[ChipGeek]

https://forums.butterflylabs.com/bfl-forum-miscellaneous/519-10-dec-2012-bfl-asic-update.html

But to cut to the chase the bottom line I read here is that you do not have the mask set done and you don't have clear understanding of the process that needs gone through to get the maskset done.

The maskset is the one huge expenditure that the ASIC foundry would be hesitant to spend unnecessarily. After the maskset is done, there is no reason not to let the train run its full course until the endstation. The costs involved are relatively minor compared to the huge upside if you happen to find yet another fault which you must correct for the next iteration.

You have clearly designed the chip too aggressively breaking some design rules that have now caused some speedbumps on the road. Professionals should have understood the design rules that need to be followed so that the speedbumps are either avoided or taken with full intent of doing so. If they come as a surprise you have at least failed to ask the right questions earlier.
Well these things you learn and next project you can do better.

What is the number one reason, why most companies are really afraid going to full-custom? I mean full-full-custom and not just standard-cell which sometimes somebody is also calling full-custom but clearly you are not doing so.
Well the reason is that ASIC projects have huge risks involved and going full custom further increases the risks exponentially. No matter where and what the risks are when they are finally realized, they still come back to the underlying rootcause of taking on the exponential risks when deciding to go full-custom. In your case I don't quite understand what was the upside gained from full-custom other than it has so expensive ring to it so it could win some preorders with that ring.

I also wonder which phase of production the fab is in.  Mask set done?  Wafers started?
Depending on the process and "hot lot" status, wafers typically take between 4 and 8 weeks.
Then there are extra days to (optionally) test the wafers, cut the wafers, package the parts, then test the final parts.  Then ship and assemble (solder) them to the boards, then test the boards.
(Please NO jokes about 4 to 6 weeks.  Above "4 to 8 weeks"  is serious.)

If the wafers come out of the fab on Jan. 10, then I would guess first SC units will ship sometime between Jan. 21 and 31.

[BitSyncom]

https://forums.butterflylabs.com/bfl-forum-miscellaneous/519-10-dec-2012-bfl-asic-update.html

But to cut to the chase the bottom line I read here is that you do not have the mask set done and you don't have clear understanding of the process that needs gone through to get the maskset done.

The maskset is the one huge expenditure that the ASIC foundry would be hesitant to spend unnecessarily. After the maskset is done, there is no reason not to let the train run its full course until the endstation. The costs involved are relatively minor compared to the huge upside if you happen to find yet another fault which you must correct for the next iteration.

You have clearly designed the chip too aggressively breaking some design rules that have now caused some speedbumps on the road. Professionals should have understood the design rules that need to be followed so that the speedbumps are either avoided or taken with full intent of doing so. If they come as a surprise you have at least failed to ask the right questions earlier.
Well these things you learn and next project you can do better.

What is the number one reason, why most companies are really afraid going to full-custom? I mean full-full-custom and not just standard-cell which sometimes somebody is also calling full-custom but clearly you are not doing so.
Well the reason is that ASIC projects have huge risks involved and going full custom further increases the risks exponentially. No matter where and what the risks are when they are finally realized, they still come back to the underlying rootcause of taking on the exponential risks when deciding to go full-custom. In your case I don't quite understand what was the upside gained from full-custom other than it has so expensive ring to it so it could win some preorders with that ring.

I also wonder which phase of production the fab is in.  Mask set done?  Wafers started?
Depending on the process and "hot lot" status, wafers typically take between 4 and 8 weeks.
Then there are extra days to (optionally) test the wafers, cut the wafers, package the parts, then test the final parts.  Then ship and assemble (solder) them to the boards, then test the boards.
(Please NO jokes about 4 to 6 weeks.  Above "4 to 8 weeks"  is serious.)

If the wafers come out of the fab on Jan. 10, then I would guess first SC units will ship sometime between Jan. 21 and 31.

I was wondering when people like you two are going to start posting. On a personal note, it is my job to view them as serious competitors, but I completely lost it when they mentioned the "chips" are on their way in 1-2 weeks but also said they are making adjustments.

fact: you can not make adjustments once the MASK is made. even if you were to run a gate/metal fix, you'd still have to run the whole process all over, which is a workflow of 2 month. This time is also completely not limited by man power, but limited to how fast the Fab can produce the layers, and this is not magic, it is mathematically calculable once you "tape-out", how fast you will get your chips back. all these are industry standard. TSMC, one of the big players in this field can produce a "super hot lot" in 0.8 days.

I didn't want to entering a fight of words originally, but I am going to say it now. they lied and I'm disappointed.

[ChipGeek]

I also wonder which phase of production the fab is in.  Mask set done?  Wafers started?
Depending on the process and "hot lot" status, wafers typically take between 4 and 8 weeks.
Then there are extra days to (optionally) test the wafers, cut the wafers, package the parts, then test the final parts.  Then ship and assemble (solder) them to the boards, then test the boards.
(Please NO jokes about 4 to 6 weeks.  Above "4 to 8 weeks"  is serious.)

If the wafers come out of the fab on Jan. 10, then I would guess first SC units will ship sometime between Jan. 21 and 31.

I was wondering when people like you two are going to start posting. On a personal note, it is my job to view them as serious competitors, but I completely lost it when they mentioned the "chips" are on their way in 1-2 weeks but also said they are making adjustments.

fact: you can not make adjustments once the MASK is made. even if you were to run a gate/metal fix, you'd still have to run the whole process all over, which is a workflow of 2 month. This time is also completely not limited by man power, but limited to how fast the Fab can produce the layers, and this is not magic, it is mathematically calculable once you "tape-out", how fast you will get your chips back. all these are industry standard. TSMC, one of the big players in this field can produce a "super hot lot" in 0.8 days.

I didn't want to entering a fight of words originally, but I am going to say it now. they lied and I'm disappointed.

This (bolded above) is actually not true.  Every time we have a new chip, we tell the fab to split the lot and hold some wafers at various stages of production.  That way if the final product has a problem that can be fixed with one or two metal layers, we can make the change, the fab makes masks for only those layers, then the held wafers restart from that point and finish in less time than the whole process.  We also sprinkle spare gates throughout the design so we can make metal changes to add gates if required for bug fixes.

Example: A 24 wafer lot.  Hold 6 wafers at 1 week, 6 more wafers at 2 weeks, 6 more at 3 weeks; finished 6 wafers come out at 4 weeks.  If the chips work as expected, we release all the wafers and the remaining 18 come out in groups of 6 wafers every week for 3 more weeks.  If we have a problem that can be fixed in the top layers of the chips, we can make a mask change and have fixed wafers in a week.  If the problem is near the bottom, we need 3 weeks for the fix.  (Note: above is simplified to make the example clearer.)

We are in sub 30nm now and we take about 5 or 6 weeks for a "super hot lot" at TSMC.  I assume older (larger) processes take less time.  But 0.8 days?  I find that impossible unless you are talking a top layer metal change for wafers that were held near the end of the process.  I cannot believe any fab in the world can go from blank wafers to finished chips in less than a few days for more than a 2 or 3 metal layer process.  Do you have a reference for the 0.8 days number?  Until I'm proven ignorant, I'm calling BS.

[BitSyncom]

This (bolded above) is actually not true.  Every time we have a new chip, we tell the fab to split the lot and hold some wafers at various stages of production.  That way if the final product has a problem that can be fixed with one or two metal layers, we can make the change, the fab makes masks for only those layers, then the held wafers restart from that point and finish in less time than the whole process.  We also sprinkle spare gates throughout the design so we can make metal changes to add gates if required for bug fixes.

Example: A 24 wafer lot.  Hold 6 wafers at 1 week, 6 more wafers at 2 weeks, 6 more at 3 weeks; finished 6 wafers come out at 4 weeks.  If the chips work as expected, we release all the wafers and the remaining 18 come out in groups of 6 wafers every week for 3 more weeks.  If we have a problem that can be fixed in the top layers of the chips, we can make a mask change and have fixed wafers in a week.  If the problem is near the bottom, we need 3 weeks for the fix.  (Note: above is simplified to make the example clearer.)

We are in sub 30nm now and we take about 5 or 6 weeks for a "super hot lot" at TSMC.  I assume older (larger) processes take less time.  But 0.8 days?  I find that impossible unless you are talking a top layer metal change for wafers that were held near the end of the process.  I cannot believe any fab in the world can go from blank wafers to finished chips in less than a few days for more than a 2 or 3 metal layer process.  Do you have a reference for the 0.8 days number?  Until I'm proven ignorant, I'm calling BS.

Missed a word there, 0.8 day per layer. I am not saying you can finish the whole chip in 0.8 days, for example our chip has 29 layers, as we released earlier this week in our development thread.

[PuertoLibre]

Shall I dig up the posts where I said the very same thing to BFL's COO and he suggested BFL could still ship in December of 2012? ...he also suggested, I was a stupid, idiotic liar, and a waste of human flesh, but that's not really relevant.

How about the email from a BFL CS rep posted to bitcointalk suggesting that BFL expects to ship late December or early January?

They're liars bud, they're not nearly ready to ship finished ASIC products and they know it.

I recall. I recall he said the same to me.

[PuertoLibre]

Wow, surprisingly flippant:

https://forums.butterflylabs.com/blogs/bfl_jody/55-so-we-get-have-holiday.html#comment389