Community Miner Design Discussion

[Mikestang]

Right now I'm hoping to have the Avalon test board prototype PCBs ordered by Friday. I should have the layout finished today, and tomorrow I'll do some verifying. I might also have a stickminer PCB prototype to add to the order; we'll see.

Wow, I can't believe I have missed this thread until now.  Looks like this is replacing the gekko science pod miner then?  Way cool, I will follow this thread anxiously as I have both and S1 and S3 that I am not using, as well as an S5 that I was going to have hosted but will now hold off until these update boards are ready.  Wicked.

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[sidehack]

Actually it's taking over the GekkoScience TypeZero project, from which I guess both the pod and Compac were tangents. It's possible the A3218 test board could become a product, but since Avalon ain't selling chips and working with pulls sucks, it's just as possible it won't. But I'm really hoping the full S1-refit boards with Bitfury chips happens in full.

[AleScamHole]

Actually it's taking over the GekkoScience TypeZero project, from which I guess both the pod and Compac were tangents. It's possible the A3218 test board could become a product, but since Avalon ain't selling chips and working with pulls sucks, it's just as possible it won't. But I'm really hoping the full S1-refit boards with Bitfury chips happens in full.

apologies for the ignorance but i have followed the thread with excitement for a while now

does this mean the project will now focus only on re-fits?
i only ask as i was one who was hoping for a pod or new sticks from you, i dont have old equipment to re-fit myself

once again, sorry for the ignorance , just wondering

[RaginglikeaBoss]

Figured it was worth asking as i have a few s5s laying around and have seen a few older stock going for insanely low prices cus they are only 1/2 hashing or somehow damaged on the boards. wanted to snatch up a few before you released your hardware and they were snapped up by everyone here.

wouldnt mind grabbing a c1 to play with. wonder if the old water cooler could keep up with the heat from new chips.

I just picked up a guys mini-farm of C1's, and boy am I glad I did now.  Parting a couple of them paid for themselves, fixed my other older tech and started slapping on water blocks to everything, haha.  I have 4-6 extra not running at the moment if you're interested, just PM me.

The idea of upgrading the blades in the C1's is beautiful.  I use a singular 720*1080 radiator for my dual S5 water cooled unit, so I really see no issue using a similar style to this with the C1 but simply adding a little more radiator space, or even simply equipping a push-pull fan system per 360*180 radiator.

[HagssFIN]

Any news from mr. Punin of BFSB Finland Oy?

[Mitak]

Nothing official, only rumors

[carlosmnk]

Nothing official, only rumors

I like thouse runors then 

[sidehack]

So, as mentioned earlier, the proof-of-concept I'm working on now is based on the Avalon A3218. As there isn't a publicly-available datasheet on the A3218, I'm assuming the protocol works about the same as documented in the A3222 datashet.

So today I started setting up a test rig to establish SPI communication with one of the chips. But I need to know what data to send it. If anyone's got advice on this, I'd be happy to hear it.

Specifically, stuff like the A3222 datasheet gives three clock configuration segments, but I don't know why. And especially a means of calculating the midstate and other preprocessed values (a0, e0, etc). I'm spending time parsing through cgminer code, but by now there's a heck of a lot of cgminer code to look through and I figure surely after 3 years of Avalon products in the wild someone knows how those calculations work. Mostly I just need a valid sample I can push to the chip and see if it talks back with something that seems in any way "correct".

And yes, if it helps motivate someone to assist a bit, I will try to implement an A3218 stickminer based around this work.

[leowonderful]

So, as mentioned earlier, the proof-of-concept I'm working on now is based on the Avalon A3218. As there isn't a publicly-available datasheet on the A3218, I'm assuming the protocol works about the same as documented in the A3222 datashet.

So today I started setting up a test rig to establish SPI communication with one of the chips. But I need to know what data to send it. If anyone's got advice on this, I'd be happy to hear it.

Specifically, stuff like the A3222 datasheet gives three clock configuration segments, but I don't know why. And especially a means of calculating the midstate and other preprocessed values (a0, e0, etc). I'm spending time parsing through cgminer code, but by now there's a heck of a lot of cgminer code to look through and I figure surely after 3 years of Avalon products in the wild someone knows how those calculations work. Mostly I just need a valid sample I can push to the chip and see if it talks back with something that seems in any way "correct".

And yes, if it helps motivate someone to assist a bit, I will try to implement an A3218 stickminer based around this work.

I absolutely LOVE stickminers!!! So excited to hear about your newest ideas, it looks like my old pentium m laptop with a 20 port usb hub is coming back soon. Loving this progress, i'm sure a product will come soon and will crush all current gen miners. I have a weird obsession with stickminers, I bought 50 U1s when they came out and sold them later for a S5. Stickminer club FTW! Best thread in the entire forum, will keep stalking this thread around and drink some virtual coffee waiting for something to buy.

[sidehack]

Additionally, https://github.com/FrankBuss/gandalf-minder/blob/master/scripts/avalonHashData.py

This was attached to an A3255 project from about two years ago, and was tested to work. Being python it's not terribly useful for anything I'd ever want to do, but I can use it as an algorithmic reference for how to generate the required hash data that gets passed into the Avalon chip. Assuming the structure hasn't changed, but according to datasheets it was the same for the first 4 generations. Of course, the returned nonce offset and endianness of everything changed several times between A3256 and A3222 so it'll be a crapshoot manipulating test values until I get something back that actually makes sense. Assuming the chip I have works.

Maybe tomorrow I'll make some headway.

[sidehack]

Also - and yes this is off topic so I'll keep it short - but if any of you trusted guys feel like lending me some dollars to help get a project or two underway in the short term, send a PM and we can discuss terms. I hate asking (y'all know I hate asking) but I'm in a bit of a bind at present and could use some help.

[Mitak]

So, as mentioned earlier, the proof-of-concept I'm working on now is based on the Avalon A3218. As there isn't a publicly-available datasheet on the A3218, I'm assuming the protocol works about the same as documented in the A3222 datashet.

So today I started setting up a test rig to establish SPI communication with one of the chips. But I need to know what data to send it. If anyone's got advice on this, I'd be happy to hear it.

Specifically, stuff like the A3222 datasheet gives three clock configuration segments, but I don't know why. And especially a means of calculating the midstate and other preprocessed values (a0, e0, etc). I'm spending time parsing through cgminer code, but by now there's a heck of a lot of cgminer code to look through and I figure surely after 3 years of Avalon products in the wild someone knows how those calculations work. Mostly I just need a valid sample I can push to the chip and see if it talks back with something that seems in any way "correct".

And yes, if it helps motivate someone to assist a bit, I will try to implement an A3218 stickminer based around this work.

Hi,
I've always used MCU to communicate with Avalon chips.
A3222 was similar to gen 2 and 3
I can dig for the code for 3222 I'll be able to do this in my old lab
It is a firmware cod in C

[sidehack]

Right now I've got it tied to an MCP2210 for simplicity. I'll eventually be using a micro (especially on the big board) but for now I wanted to cut down on the complexity and establish basic functionality.

[Mitak]

Yep for single chip nanofury style is ok.
I ever did single chip.
Again I'm sorry I  do not have access from here to the  C code
But if you still need it I will be able to send it in a day or two

[sidehack]

Single chip is all I'm worried about right now. I'll figure out multi-chip once I get one talking.

What micro were you coding for?

[Gyrsur]

Nothing official, only rumors

what for rumors?

[sidehack]

Looks like the plan for a multi-chip Avalon board to test concept on has kinda dried up. The plan is still moving forward to build a thing or three around Bitfury chips, I just won't have to work on a big Avalon board while juggling everything else. That's fine.

I might put together a BM1384 proof-of-concept if I get some extra prototyping dollars, if nothing else to be a good load test of the power systems. It's a chip I'm pretty comfortable with by now. I do have some plans for Avalon stuff, and am still gonna be poking and prodding a bit, but probably nothing large-scale.

On a tangential note, I have about 11BTC I'd like to convert into USD if anyone's interested. Too bad Sunstone and Digi-Key don't accept bitcoins.

[kilo17]

So I have been informed that Sample chips went out to the big dogs last week, I am trying to get as hold of a few of those to get things going. 

PUNIN- maybe you can send me some of those sample chips that went out last week instead of the 1 BTC - I will double post this on the Bitfury thread in case you do not look here 

[sidehack]

Sample chips would be pretty sexy. Right now I'd be satisfied with datasheets on the ASIC and their comm chip, including some protocol details.

[ATCkit]

I'm quite interested in this project.

sidehack, are you needing anymore funds to help with development?

Man, I sure hope Bitfury gets something to you soon.  Otherwise, those chips will have to be a lot cheaper as each week goes by.