BFL ready to ship?

[dropt]

After all he is a specialist payed with 1000$/day to spot this kind of problems.

I can't comment on the validity of his statements, but ~1000/day isn't unheard of.

[Bogart]

Guys, relax.
There won't be much thermal cycling as a typical miner will be on 100% of the time.
Unlike a typical PC which is turned on once a day and turned off once a day.

It won't take much either.  Just the normal day to night swings will do it.  I have seen 100s of thousands of underfilled chips over 10 process generations, many with underfill defects, and none of them looked as bad as these.

The black blotch shown on greyhawk's zoom is a scrap part.  That is underfill, it will prevent proper cooling and is impossible to sand off without cracking the brittle silicon.

Even a few seconds of downtime will cause a huge thermal swing in such a chip.  Imagine a pool server that's overloaded, or a flaky internnet connection.

Here are some temperature graphs from a couple of my GPU miners.  The first one has a better internet connection than the second.

[johnyj]

I like this picture, where is it come from?

http://www.youtube.com/watch?v=AHyN8PizZVY

So much fun!! I will watch the whole serie 

[mobodick]

Good god

What, they didn't apply the glue that holds the metal caps in place evenly?
 

[greyhawk]

It's apparently a rush job on the underfill. If it looks like that on the edges I don't even want to know how many voids will be underneath those things.

Of course according to Josh those are JPG artifacts, nothing to worry about, everything's fine in Butterfly Land.

If only he knew how JPG artifacts look like.

(Hint: Nothing like this. I can tell by the pixels and having seen quite some artifacts in my time)

I'm joking of course, though not about the underfill and Josh's limited understanding of image compression.

[ChipGeek]

What, they didn't apply the glue that holds the metal caps in place evenly?
 

In these FCBGA packages there are no metal caps.  The shiny square you see is the back of the actual silicon chip itself.  Since these are quickly assembled prototypes, I would not weigh any possible defects in the underfill too heavily. 

Yes it is true that poor underfill will cause long term reliability problems in the production parts.  What you see photos of here are not the production parts - just test units from the first production run.  In other words, I'm guessing these are likely units they made while they were refining the underfill process.

[ChipGeek]

Enigma pointed to strange looking soldering points, but:
- they surely use mostly the edge pins of the chip (because of quick QFN to FCBGA conversion), leaving  most of the middle pins unused;
- Enigma used a photo of a board which was put through the oven without chips, not the one just prepared to place them;
- the photo was blurry and unfocused, so Enigma's conclusions are plain guesswork.

I have a comment for each of your 3 points.

1) This is simply wrong.  When converting from QFN to FCBGA, the upper layer of metal on the silicon is changed to a miniature version of the BGA package.  Proof of this is the photos of the wire bonding test die.  The attachment points are (now) in an array, not along the edge.  Note that the die can have typically more or sometimes less connections than the final BGA package.  The BGA package is simply a very tiny multi-layer PCB that translates the chip balls/bumps to the package ball grid on the bottom.

2) True as far as I can tell.

3) Guesswork?  Maybe.  Maybe not.

I will add that putting vias in the middle of the BGA pads can be problematic.  But I know of assembly houses that can effectively and properly deal with this.  Another option is to get the blank boards with filled vias.  (Not something that the PCBs in the photos have.)  We recently had to do this on a project I'm working on.

[SgtSpike]

Good god

What, they didn't apply the glue that holds the metal caps in place evenly?
 

That's what I was thinking... it's just uneven glue (or epoxy, or whatever it's called in this case).  If you look at edges other than the top, you can see similar unevenness, but it's clear that it is because of the glue.  The left side of the bottom left chip in this zoom is an excellent example.

[Miner99er]

For reference...

http://imgur.com/sicFhlY

not very even at all, but better than the BFL chips... and those chips aren't clocking as high as this Athlon did.

Conclusion: We're going to have to wait and see.

[RHA]

- they surely use mostly the edge pins of the chip (because of quick QFN to FCBGA conversion), leaving  most of the middle pins unused;

1) This is simply wrong.  When converting from QFN to FCBGA, the upper layer of metal on the silicon is changed to a miniature version of the BGA package.  Proof of this is the photos of the wire bonding test die.  The attachment points are (now) in an array, not along the edge.  Note that the die can have typically more or sometimes less connections than the final BGA package.  The BGA package is simply a very tiny multi-layer PCB that translates the chip balls/bumps to the package ball grid on the bottom.

I wrote this just because of where the wires went on the photo of test die. Mostly the edge pins, most of the middle pins were left unused, so I concluded they have done it to avoid big changes of their PCB (miner's one, not BGA's one).
But I agree - it could be because of difficulty of wiring the middle pins.