DIY PCB with AVALON: "The Quarter Stick" - Needs Help!

[dieguito]

I would be pleased if anyone could make detailed pictures of the avalon board with the asics, power stages, etc.

I would like to start developing as soon as possible.

Regards

Knecke

https://en.bitcoin.it/wiki/Avalon

These aren't adequate. I looked carefully at the board photo and you can identify some pins but some parts go out of focus and it's impossible to follow traces to figure out most pins. A direct overhead flat shot showing a larger area of the board would be ideal.

I don't think any Avalon owner is likely to start showing off photos as it's counter productive to them. Still it would be nice.

We bought a broken Avalon to disect it and will gladly post pictures.

All the best,
Dieguito

[roybitcoin]

Would a cheap small reflow oven like this one be OK?

http://www.ebay.com/itm/400325274614

This would probably be ok, but if you just want to make them for own use, and not populate a great amount of boards, you could probably get by using the hotplate technique i linked above. At the moment i'm not 100% sure that it would work flawlessly, but i'm going to test this. If it does, we would have no problem populating the boards by our self, without expensive equipment.

It would be very useful if whoever makes boards could supply stencils as well.

I´ll follow all the DIY projects and help in anything I can. I have ordered 20 ASICS from Zefir and I´m very interested in this subject but I´m very new to bitcoins.

I´ll start a DIY ASIC project with 2 colleagues. We are EE and work at a R&D Dep (15+ years of experience). We have an old reflow oven and work very well (850 from Manncorp). For solder paste we use a manual pick and place (from manncorp too) and not stencil. That is only for small assemblies.

Best regards!

[Bogart]

I would be pleased if anyone could make detailed pictures of the avalon board with the asics, power stages, etc.

I would like to start developing as soon as possible.

Regards

Knecke

https://en.bitcoin.it/wiki/Avalon

These aren't adequate. I looked carefully at the board photo and you can identify some pins but some parts go out of focus and it's impossible to follow traces to figure out most pins. A direct overhead flat shot showing a larger area of the board would be ideal.

Some more photos here:

https://bitcointalk.org/index.php?topic=153511.0

I don't know if those are any more adequate or not.  Note the links to full-resolution versions at the end of the post.

[BkkCoins]

We bought a broken Avalon to disect it and will gladly post pictures.

That would be very cool!

For solder paste we use a manual pick and place (from manncorp too) and not stencil. That is only for small assemblies.

How does that work. Do you dip the parts in paste and then place them with tweezers? Or something like that...

Some more photos here:

https://bitcointalk.org/index.php?topic=153511.0

I don't know if those are any more adequate or not.  Note the links to full-resolution versions at the end of the post.

Checking this out now. Thx.
edit: Much more detail. Too bad data signal traces are internal layers. Can see power connections more clearly, and less ambiguity. Top pane appears to be 1.2V and can see crystal is 32.0 MHz.

[atcsecure]

I would be pleased if anyone could make detailed pictures of the avalon board with the asics, power stages, etc.

I would like to start developing as soon as possible.

Regards

Knecke

https://en.bitcoin.it/wiki/Avalon

These aren't adequate. I looked carefully at the board photo and you can identify some pins but some parts go out of focus and it's impossible to follow traces to figure out most pins. A direct overhead flat shot showing a larger area of the board would be ideal.

I don't think any Avalon owner is likely to start showing off photos as it's counter productive to them. Still it would be nice.

agreed, I came to the same conclusion, we need to nail down a design/cost/# of chips

[roybitcoin]

For solder paste we use a manual pick and place (from manncorp too) and not stencil. That is only for small assemblies.

How does that work. Do you dip the parts in paste and then place them with tweezers? Or something like that...

You place points of solder paste over the pads with a tip (it uses air compressor). After that you place the parts with tweezers or with another tip with air suction. Look this model, we have an older one but very similar.

http://www.manncorp.com/smt/prod-179/smt-place-2000-manual-pick-and-place.html

[BkkCoins]

You place points of solder paste over the pads with a tip (it uses air compressor). After that you place the parts with tweezers or with another tip with air suction. Look this model, we have an older one but very similar.

Interesting. I didn't know they made machines like that.

***

Here is my notes on inspecting board photo to determine pinout. Of course, the critical pins (data i/o) are hidden in vias so cannot be determined exactly. I just did this for fun, to figure it out. Please comment if you notice an error in my judgement.

[daemondazz]

Nice, it'd be good to see how close you are

[hak8or]

I am also very interested in joining these efforts! I am an EE hobbyist but very eager to play around with these chips. Luckily these chips are QFN, which is a godsend compared to BGA. This also means we can use OSH park for prototypes all the way up to 4 layers for cheap.

Some quick questions:

https://en.bitcoin.it/wiki/Avalon <-- is this a good repository of everything we know so far?

Has anyone stuck a scope on one of these chips and checked out the signals?

Did anyone decap the chip yet and get photos? If not, seeing as how this ic is only 110nm, we should be able to send a few chips to a decap plant and have them decap it properly and get high quality images only for a few grand. For a few grand more, they should be able to reverse engineer it a bit for us too.

I see BkkCoins has done some chip pin inspecting. Do you have any oscope close by so we can get the clock frequency? Some multimeters have a frequency counter.

Anyways, I would gladly help out designing the PCB for these chips. I have Altium on hand and can make a few prototypes. I actually wonder if someone who has an Avalon can sell one of the modular units? Then the dev's can send it to each other every few days to take turns trying to find out as much information as possible.

[dieguito]

I am also very interested in joining these efforts! I am an EE hobbyist but very eager to play around with these chips. Luckily these chips are QFN, which is a godsend compared to BGA. This also means we can use OSH park for prototypes all the way up to 4 layers for cheap.

Some quick questions:

https://en.bitcoin.it/wiki/Avalon <-- is this a good repository of everything we know so far?

Has anyone stuck a scope on one of these chips and checked out the signals?

Did anyone decap the chip yet and get photos? If not, seeing as how this ic is only 110nm, we should be able to send a few chips to a decap plant and have them decap it properly and get high quality images only for a few grand. For a few grand more, they should be able to reverse engineer it a bit for us too.

I see BkkCoins has done some chip pin inspecting. Do you have any oscope close by so we can get the clock frequency? Some multimeters have a frequency counter.

Anyways, I would gladly help out designing the PCB for these chips. I have Altium on hand and can make a few prototypes. I actually wonder if someone who has an Avalon can sell one of the modular units? Then the dev's can send it to each other every few days to take turns trying to find out as much information as possible.

With my partners we bought a broken Avalon and I can check with them to provide a blade for inspection so we learn as much as possible while the specs get to us.

All the best,
Dieguito

[samurai1200]

Wow this thread really exploded. Unfortunately, I couldn't get myself to read it all (just allten and burnin's posts)   

Anyway, with regard to Avalon ASIC pinout, if it would be any help I can give you informed guesses for some pins:

Guesses are based on: https://en.bitcoin.it/w/images/en/c/cb/Avalon-detail.JPG


1. GND pins -- assuming the chip side copper pour is gnd (more on this after), you can see that pins (counter clockwise from pin 1 dot) # 3,4,6(?),11,12,13,14,15,16,19,21,22,25,26,27,28,31,33,34,39,40,41,43,46,47,48 are connected to the pour.

It is equally likely that these pins are for PWR, since it is highly likely that the thermal pad is the singular (or at least the MAIN) GND. Thermal pads being connected to GND is standard practice.

HOWEVER, placing two decoupling caps near each other that are a decade apart in capacitance is a common way to get rid of a wide band of PSU noise. I see this at pins 7,24,37. Three 10-mil traces could easily carry 2A (=2.4 watts) with ~10C rise in trace temp. This could mean that the top copper pour is indeed ground.

2. CLKin signal speeds -- I believe the clock feeding the Avalon is lower speed (hinting at an internal PLL/divider). This is more of a guess. In the above photo, you can see an exposed test point titled "CK," common shorthand for CLOCK. Since this is single-ended, it is likely that the line is below 100 MHz.

However, this could simply be a test point/pin for an internal LO, and the real clock signal could be coming in differentially on any of the pairs that look purposefully impedance-matched (1&2, 17&18, 29&30), though I think its more likely that these are data lines of some sort.

[E3V3A]

@allten:
I have access to X-ray equipment so if you need any help seeing "what's inside", just send me the HW to be x-rayed (send me a PM for instructions).

[hak8or]

Wow this thread really exploded. Unfortunately, I couldn't get myself to read it all (just allten and burnin's posts)   

Anyway, with regard to Avalon ASIC pinout, if it would be any help I can give you informed guesses for some pins:

Guesses are based on: https://en.bitcoin.it/w/images/en/c/cb/Avalon-detail.JPG

1. GND pins -- assuming the chip side copper pour is gnd (more on this after), you can see that pins (counter clockwise from pin 1 dot) # 3,4,6(?),11,12,13,14,15,16,19,21,22,25,26,27,28,31,33,34,39,40,41,43,46,47,48 are connected to the pour.

It is equally likely that these pins are for PWR, since it is highly likely that the thermal pad is the singular (or at least the MAIN) GND. Thermal pads being connected to GND is standard practice.

HOWEVER, placing two decoupling caps near each other that are a decade apart in capacitance is a common way to get rid of a wide band of PSU noise. I see this at pins 7,24,37. Three 10-mil traces could easily carry 2A (=2.4 watts) with ~10C rise in trace temp. This could mean that the top copper pour is indeed ground.

I am not too sure that the top pour is ground. Look at how the DC-DC converter on the right seems to have the capacitors positive legs connected to the top pour.

Not to mention, I think that the DC-DC converter is a buck converter seeing as how the chip uses 3.3v io voltage and the standard 1.2v for the core. I am assuming that the 1.2v core is what does the actual hashing and whatnot, resulting in it using more power. It does not make much sense to be sending all the required power over the 1.2v rail due to I^2R losses, so the DC-DC converter is likely buck, going from a much higher voltage like 12v down to the 1.2v required for the core. Assuming the converter is indeed buck, then the diodes ... never mind about using the converters diode setup to further push my idea that the top pour is power, the diode setup (specifically D1) seems alien to me.

Anyways, looking at the mosfets (Q1, Q3, Q4), they are all 24v fets, so it is quite possible the converter is a buck that gets 1.2v from a 12v rail. Since in buck converters the inductor is connected to the power rail, and looking at how the inductor on the board is connected to the top pour, I feel somewhat safe saying how the top pour is the main 1.2v power pour.

I was using this image for my information:
http://avalon.mystisland.org/a14.jpg

Regarding your idea that the clock input is most likely a low frequency due to it not being differential, I completely agree. Though, this is weird as hell, where the heck are the oscillators? I can't see them anywhere, heh. Possibly on the other side of the PCB? That would be wierd though, considering how much empty space there is on the top, and how much more it costs to get components on both sides of the PCB.

Also, apologies, but I must go to class now for the next few 12 hours and won't be able to reply for a while.

[BkkCoins]

Top pour is definitely 1.2V. Not only from indications of diode, inductor and caps but also because there is a test point labeled 1P2V that connects directly to the pour.

Large thermal pad with thermal vias is under the chip. I'm guessing that most of the N/C pins are actually connected inwards to GND pad. I'm also presuming that the pins that come out and have two caps (decoupling pairs) are 3.3V since that power is only needed for I/O interface it probably needs very little trace width. There is a 3P3V test point next to the regulator but as with data signals they all go submarine on us.

To me the only thing that needs figuring out still is what data lines are what, and the actual connection arrangement for bypass, in, out. Probably a daisy chain ( in1 > bypass > in2 > etc.) But then what about result outs? Do they all wire OR back to the controller or does each line go back separately (there are a lot of pins on the back plane, 20 I believe) or some other deal. Or maybe these are all I2C as that would be two lines bi-directional. From what I saw on Icarus he used normal UART style serial lines and maybe it's just as simple here.

All this is just a fun exercise because the details will soon be revealed in plenty of time to do board designs and make boards before the chips ever arrive. So don't go off all nutty about decapping chips and spending too much effort on this.

If the plans end up not being open sourced and we're all stuck up the creek then we can get serious.

[Knecke]

This Multilayer s**t, on old PCBs you followed the trace and saw where it is connected but here you cant see shit ^^

Ok we know there are serial DATA in/out, and CLK, maybe Debugs.

I assume the chip hashes <???and compares and if it found something it gives a reply???>.
because it wouldn be possible to stream the data out of the asic and compare them in the fpga.

Ok lets wait for official datasheets and layouts.

[BkkCoins]

I assume the chip hashes <???and compares and if it found something it gives a reply???>.
because it wouldn be possible to stream the data out of the asic and compare them in the fpga.

Yes, when a target hash is found it outputs a serial stream. But remember there are 10 chips on each sub-module board. I believe the work is streamed in serially thru all 10 chips. I say this because that's how the driver outputs the work - as a long stream where each portion is a range of work for each chip. But when a result occurs it has to collect/monitor from all 10 chips. I would guess that a wire'OR type return path could be used as long as a collision doesn't occur, or can be detected. Otherwise you have 10 output lines coming back and each needs to polled for detecting data. I'm speculating here.

Someone with an Avalon could look at the back plane edge connectors and see if there are 12+ data signals, or 4 data signals, that all route back into the fpga. I find this a bit of a strange design - if this is how it's done, to use the huge pin count of an fpga for monitoring 80 chips outputs.

My plan would be to put a PIC locally for each 8-10 chips and use it as in intelligent I2C controller that can talk to a RasPi as miner running cgminer (I2C protocol is available on RaspPi). That's just my current idea and will see when more details emerge. This way the miner justs sends work to each board using I2C and the board can split the work for it's chip count and shift it into the chips, collect results and send back to miner using I2C again. Very little data over I2C but enough to make work happen.

[Knecke]

A solution which uses a Rasppi would be great.

I wonder how the work is shared, in order that the asics not calculate the same hashes at the same time,
maybe you send the work with a modified nonce to each chip?

[BkkCoins]

A solution which uses a Rasppi would be great.

I wonder how the work is shared, in order that the asics not calculate the same hashes at the same time,
maybe you send the work with a modified nonce to each chip?

The cgminer Avalon driver splits the nonce into ranges. So it divides the max nonce by the number of chips and then multiplies that value by the chip number (eg. 0..9) and shifts it out to the chips. Each chip starts at that value and hashes until it's range is done. I'm not sure it knows it's done but probably it just hashes until more work is sent. I think I saw some cgminer code that decides how long to wait per nonce but I'm hazy on it at the moment.

(Obviously I'm not familiar with the chip circuitry but a simple way to do this is a shift register / counter. You can shift in a start value and then start clocking it to count up. You get spurious hashes during the shifting but it doesn't matter as you'll ignore any outputs during that time. Well, there is pipelining, so you ignore until the pipeline is valid.)

[BitHav]

Hi everybody,

As the soldering of the ASICs (and other components) to the PC Boards requires some expertise, not only to not destroy or tamper the reliability of the chips with the initial soldering process, but also for the life of the working boards (a faulty or improper soldered board can work initially, but depending on the quality of the soldering process, its expectancy of life could be greatly reduced).

I can help with the production of the pcbs for the ASICS. I can order the pcbs and the other components (Except for the Avalon ASIC), populate the boards (assembly) and return them already tested. It can be done at cost (cost of pcbs, components, assembly and testing) plus a small fee that will be added.

Interested members can send me the chips, and after a few days, I will return tested, working boards.

Is this of interest to anybody?

[daemondazz]

Quite a few people with an EE background or experience doing this, sounds good!