Custom RAM Timings for GPU's with GDDR5 - DOWNLOAD LINKS - UPDATED

[kilo17]

This is starting to become: "who has the biggest ****"..

Mine isn't, it's probably thickest   

LOL --

I am actually more interested in HBM than GDDR5 but thats a different thread at a later date.  Back on track, some of the timings are definitely out of whack, I hope to have some shots to put up tomorrow of improvements but it is a painstaking process with Samsung

[kilo17]

This is starting to become: "who has the biggest ****"..

Mine isn't, it's probably thickest    

LOL --

I am actually more interested in HBM than GDDR5 but thats a different thread at a later date.  Back on track, some of the timings are definitely out of whack, I hope to have some shots to put up tomorrow of improvements but it is a painstaking process with Samsung

I know the formats of HBM and HBM2. However, here's a challenge-response.

MC_SEQ_RAS_TIMING: 0x1076c00

What is the value of tFAW32? Both the raw representation, and what it truly means. It's already in little endian.

I like a challenge- maybe you can step up and answer one of Brewins questions, it appears the others do not want to play (or cannot play -lol) -

I will take a gander at the challenge later tonight.  I am looking into what appears to be an error in the 1625 Strap for Samsung Memory the tRFC.  Either I have made an error or AMD made an error.  All the other straps check out except that one value.  If you have some input into that particular value I would appreciate it.  Not sure but it appears that value is the default hex code from AMD.  It seems to work in the strap.

ps- I know it is the Four Active Window and is the time word lines can be opened in four banks

[jstefanop]

I think I'm just going to post source to decoding app I built...mostly because I think the community will be able to figure out optimal values far quicker than the three of us Im kind of tired of iterating over the hundreds of timing possibilities (and thats just on one algo).

[zigun]

Start digging this stuff too, is to hard to find any timing information in GDDR5 specification reference material?

[Eliovp]

Start digging this stuff too, is to hard to find any timing information in GDDR5 specification reference material?

The Mode Registers help.

For example

[Metroid]

I had great results few months ago, making hynix to have elpida performance in few algo, + hynix had an even great performance with my own custom latency numbers.

[zigun]

I had great results few months ago, making hynix to have elpida performance in few algo, + hynix had an even great performance with my own custom latency numbers.

How many hours did u spend? Any advices? )

[EuroCanuck]

sorry to sound like a begger but i would really love some timings for a rx470 4g with elpida if your willing to share.

[dallase]

I had great results few months ago, making hynix to have elpida performance in few algo, + hynix had an even great performance with my own custom latency numbers.

I've gotten over 900H/s stable on XMR with my 470 4G - so yeah, it's pretty nice.

I assume thats overclock + custom timings? 

Whats best rate on underclock/undervolt + custom timings?

[Metroid]

I had great results few months ago, making hynix to have elpida performance in few algo, + hynix had an even great performance with my own custom latency numbers.

How many hours did u spend? Any advices? )

I was not happy with the hynix performance on few algo so i decided to create my own, I spent 15 minutes. I do have a PHD in computer Science.

I had great results few months ago, making hynix to have elpida performance in few algo, + hynix had an even great performance with my own custom latency numbers.

I've gotten over 900H/s stable on XMR with my 470 4G - so yeah, it's pretty nice.

If you got that at 0.850v then it was a miracle. All my cards use 0.850v and I could not achieve that.

[zigun]

You guys are funny, I bet none of you have figured out all 20 of those timings.  It is tough as shit to figure out- here's a challenge for you 3-  if you kilo, jstefanop  and eliovp can each post one of the following 3 timings from The Stilts Hyinx 1250 strap- I will then be a believer, otherwise I say you're all full of shit/

1 - tWR
2 - tWTR
3 - tRCDR


Good luck

 - that's funny.  I will do one- how about tWTR - it really doesn't matter to me

I changed my mind, I am going to post the tRTW to prevent giving away to much info -  the tRTW in the following Stilt strap is 21

77 71 33 20 00 00 00 00 08 39 47 2A 50 55 0C 0B 24 20 45 04 00 46 C4 00 22 BB 1C 00 5C 0B 14 20 4A 89 00 A0 00 00 01 20 12 0C 21 1E 51 19 26 13

tRCDR - 0xE.

Correct me if I wrong, based on compare of custom straps from The Stilt with original one. Timing info contain in the string  77 71 33 20 00 00 00 00 08 39 47 2A and possible it's magic 3 registers one of them last or first is MC_SEQ_RAS_TIMING

[kilo17]

I had great results few months ago, making hynix to have elpida performance in few algo, + hynix had an even great performance with my own custom latency numbers.

How many hours did u spend? Any advices? )

I was not happy with the hynix performance on few algo so i decided to create my own, I spent 15 minutes. I do have a PHD in computer Science.

I had great results few months ago, making hynix to have elpida performance in few algo, + hynix had an even great performance with my own custom latency numbers.

I've gotten over 900H/s stable on XMR with my 470 4G - so yeah, it's pretty nice.

If you got that at 0.850v then it was a miracle. All my cards use 0.850v and I could not achieve that.

Couple of questions -
1- Are you Hex editing or using Polaris Bios Editor? 
2- How many watts are you pulling at the wall (no one cares about the 0.85v because it doesn't mean much)
3- What changes did you make to the latency, was it tRCD, tRCDW, tRC, tWTR .......etc?

Thanks

[kilo17]

You guys are funny, I bet none of you have figured out all 20 of those timings.  It is tough as shit to figure out- here's a challenge for you 3-  if you kilo, jstefanop  and eliovp can each post one of the following 3 timings from The Stilts Hyinx 1250 strap- I will then be a believer, otherwise I say you're all full of shit/

1 - tWR
2 - tWTR
3 - tRCDR


Good luck

 - that's funny.  I will do one- how about tWTR - it really doesn't matter to me

I changed my mind, I am going to post the tRTW to prevent giving away to much info -  the tRTW in the following Stilt strap is 21

77 71 33 20 00 00 00 00 08 39 47 2A 50 55 0C 0B 24 20 45 04 00 46 C4 00 22 BB 1C 00 5C 0B 14 20 4A 89 00 A0 00 00 01 20 12 0C 21 1E 51 19 26 13

tRCDR - 0xE.

Correct me if I wrong, based on compare of custom straps from The Stilt with original one. Timing info contain in the string  77 71 33 20 00 00 00 00 08 39 47 2A and possible it's magic 3 registers one of them last or first is MC_SEQ_RAS_TIMING

MC_SEQ_RAS_TIMING is a bunch of timings, not just 1.   

[zigun]

You guys are funny, I bet none of you have figured out all 20 of those timings.  It is tough as shit to figure out- here's a challenge for you 3-  if you kilo, jstefanop  and eliovp can each post one of the following 3 timings from The Stilts Hyinx 1250 strap- I will then be a believer, otherwise I say you're all full of shit/

1 - tWR
2 - tWTR
3 - tRCDR


Good luck

 - that's funny.  I will do one- how about tWTR - it really doesn't matter to me

I changed my mind, I am going to post the tRTW to prevent giving away to much info -  the tRTW in the following Stilt strap is 21

77 71 33 20 00 00 00 00 08 39 47 2A 50 55 0C 0B 24 20 45 04 00 46 C4 00 22 BB 1C 00 5C 0B 14 20 4A 89 00 A0 00 00 01 20 12 0C 21 1E 51 19 26 13

tRCDR - 0xE.

Correct me if I wrong, based on compare of custom straps from The Stilt with original one. Timing info contain in the string  77 71 33 20 00 00 00 00 08 39 47 2A and possible it's magic 3 registers one of them last or first is MC_SEQ_RAS_TIMING

MC_SEQ_RAS_TIMING is a bunch of timings, not just 1.   

Ofc it's a 32 bit register where each value 4 bit. I've just want to know where exactly in this 48 byte strap this register. Also what about MC_SEQ_CAS_TIMING register, any interesting there?

[zigun]

You guys are funny, I bet none of you have figured out all 20 of those timings.  It is tough as shit to figure out- here's a challenge for you 3-  if you kilo, jstefanop  and eliovp can each post one of the following 3 timings from The Stilts Hyinx 1250 strap- I will then be a believer, otherwise I say you're all full of shit/

1 - tWR
2 - tWTR
3 - tRCDR


Good luck

 - that's funny.  I will do one- how about tWTR - it really doesn't matter to me

I changed my mind, I am going to post the tRTW to prevent giving away to much info -  the tRTW in the following Stilt strap is 21

77 71 33 20 00 00 00 00 08 39 47 2A 50 55 0C 0B 24 20 45 04 00 46 C4 00 22 BB 1C 00 5C 0B 14 20 4A 89 00 A0 00 00 01 20 12 0C 21 1E 51 19 26 13

tRCDR - 0xE.

Correct me if I wrong, based on compare of custom straps from The Stilt with original one. Timing info contain in the string  77 71 33 20 00 00 00 00 08 39 47 2A and possible it's magic 3 registers one of them last or first is MC_SEQ_RAS_TIMING

MC_SEQ_RAS_TIMING is a bunch of timings, not just 1.   

Ofc it's a 32 bit register where each value 4 bit. I've just want to know where exactly in this 48 byte strap this register. Also what about MC_SEQ_CAS_TIMING register, any interesting there?

Each value is not 4-bit, just some of them are.

SEQ_RAS [2 2 14 14 2 42] right?

[kilo17]

You guys are funny, I bet none of you have figured out all 20 of those timings.  It is tough as shit to figure out- here's a challenge for you 3-  if you kilo, jstefanop  and eliovp can each post one of the following 3 timings from The Stilts Hyinx 1250 strap- I will then be a believer, otherwise I say you're all full of shit/

1 - tWR
2 - tWTR
3 - tRCDR


Good luck

 - that's funny.  I will do one- how about tWTR - it really doesn't matter to me

I changed my mind, I am going to post the tRTW to prevent giving away to much info -  the tRTW in the following Stilt strap is 21

77 71 33 20 00 00 00 00 08 39 47 2A 50 55 0C 0B 24 20 45 04 00 46 C4 00 22 BB 1C 00 5C 0B 14 20 4A 89 00 A0 00 00 01 20 12 0C 21 1E 51 19 26 13

tRCDR - 0xE.

Correct me if I wrong, based on compare of custom straps from The Stilt with original one. Timing info contain in the string  77 71 33 20 00 00 00 00 08 39 47 2A and possible it's magic 3 registers one of them last or first is MC_SEQ_RAS_TIMING

MC_SEQ_RAS_TIMING is a bunch of timings, not just 1.   

Ofc it's a 32 bit register where each value 4 bit. I've just want to know where exactly in this 48 byte strap this register. Also what about MC_SEQ_CAS_TIMING register, any interesting there?

Each value is not 4-bit, just some of them are.

SEQ_RAS [2 2 14 14 2 42] right?

no

[dallase]

SEQ_RAS [2 2 14 14 2 42] right?

edited... think i messed up b4

TNOPW   1 
TNOPR   0
TR2W    21
TR2R    1 
TW2R   6 
TCL      19 

[Zorg33]

I also spent almost two days already on this matter and it is though indeed...
I think I could identify RAS and CAS timing 32 bit straps and also some of the individual timings in them, but...
I can't find the Hynix AJR datasheet, (i'm using the AFR one), and I also can't find the register reference guide for the polaris GPU (or even the Sea Islands series would be great).
Any hints?

[dallase]

I also spent almost two days already on this matter and it is though indeed...
I think I could identify RAS and CAS timing 32 bit straps and also some of the individual timings in them, but...
I can't find the Hynix AJR datasheet, (i'm using the AFR one), and I also can't find the register reference guide for the polaris GPU (or even the Sea Islands series would be great).
Any hints?

Code:

MC_SEQ_RAS_TIMING - RW - 32 bits - MCIND:0x61
TRCDW    4:0 5bit    Number of cycles from active to write
TRCDWA   9:5 5bit    Number of cycles from active to write with auto-precharge
TRCDR  14:10 5bit    Number of cycles from active to read
TRCDRA 19:15 5bit    Number of cycles from active to read with auto-precharge 
TRRD   23:20 4bit    Number of cycles from active bank a to active bank b
TRC    30:24 7bit    Number of cycles from active to active/auto refresh

#define MC_SEQ_RAS_TIMING_LP__TRCDW_MASK 0x1f
#define MC_SEQ_RAS_TIMING_LP__TRCDW__SHIFT 0x0     5 bits

#define MC_SEQ_RAS_TIMING_LP__TRCDWA_MASK 0x3e0
#define MC_SEQ_RAS_TIMING_LP__TRCDWA__SHIFT 0x5    5 bits

#define MC_SEQ_RAS_TIMING_LP__TRCDR_MASK 0x7c00
#define MC_SEQ_RAS_TIMING_LP__TRCDR__SHIFT 0xa     5 bits

#define MC_SEQ_RAS_TIMING_LP__TRCDRA_MASK 0xf8000
#define MC_SEQ_RAS_TIMING_LP__TRCDRA__SHIFT 0xf    5 bits

#define MC_SEQ_RAS_TIMING_LP__TRRD_MASK 0xf00000
#define MC_SEQ_RAS_TIMING_LP__TRRD__SHIFT 0x14     4 bits

#define MC_SEQ_RAS_TIMING_LP__TRC_MASK 0x7f000000
#define MC_SEQ_RAS_TIMING_LP__TRC__SHIFT 0x18      7 bits


MC_SEQ_CAS_TIMING - RW - 32 bits - MCIND:0x62
TNOPW    1:0 2bit    Extra cycle(s) between successive write bursts
TNOPR    3:2 2bit    Extra cycle(s) between successive read bursts
TR2W     8:4 5bit    Read to write turn
TCCDL   11:9 3bit    Cycles between r/w from bank A to r/w bank B.
TR2R   15:12 4bit    Read to read time
TW2R   20:16 5bit    Write to read turn
----   23:21 3bit    Unused.
TCL    28:24 5bit    CAS to data return latency


#define MC_SEQ_CAS_TIMING_LP__TNOPW_MASK 0x3
#define MC_SEQ_CAS_TIMING_LP__TNOPW__SHIFT 0x0    # 2 bit

#define MC_SEQ_CAS_TIMING_LP__TNOPR_MASK 0xc
#define MC_SEQ_CAS_TIMING_LP__TNOPR__SHIFT 0x2    # 2 bit

#define MC_SEQ_CAS_TIMING_LP__TR2W_MASK 0x1f0
#define MC_SEQ_CAS_TIMING_LP__TR2W__SHIFT 0x4     # 5 bit

#define MC_SEQ_CAS_TIMING_LP__TCCDL_MASK 0xe00
#define MC_SEQ_CAS_TIMING_LP__TCCDL__SHIFT 0x9    # 3 bit

#define MC_SEQ_CAS_TIMING_LP__TR2R_MASK 0xf000    # 4 bit
#define MC_SEQ_CAS_TIMING_LP__TR2R__SHIFT 0xc     

#define MC_SEQ_CAS_TIMING_LP__TW2R_MASK 0x1f0000  # 5 bit
#define MC_SEQ_CAS_TIMING_LP__TW2R__SHIFT 0x10

#define MC_SEQ_CAS_TIMING_LP__TCL_MASK 0x1f000000 # 5 bit
#define MC_SEQ_CAS_TIMING_LP__TCL__SHIFT 0x18 


MC_SEQ_MISC_TIMING - RW - 32 bits - MCIND:0x63

TRP_WRA   5:0  6bit   From write with auto-precharge to active - 1.
----      7:6  2bit   Unused
TRP_RDA  13:8  6bit   From read with auto-precharge to active - 1.
----    16:14  3bit   Unused
TRP     19:16  4bit   Precharge command period - 1.
TRFC    26:20  7bit   Auto-refresh command period - 1.
TCKE    31:28  4bit   CKE power down exit timer.

#define MC_SEQ_MISC_TIMING_LP__TRP_WRA_MASK 0x3f     
#define MC_SEQ_MISC_TIMING_LP__TRP_WRA__SHIFT 0x0        # 6 bit
 
#define MC_SEQ_MISC_TIMING_LP__TRP_RDA_MASK 0x3f00
#define MC_SEQ_MISC_TIMING_LP__TRP_RDA__SHIFT 0x8        # 6 bit

#define MC_SEQ_MISC_TIMING_LP__TRP_MASK 0xf8000
#define MC_SEQ_MISC_TIMING_LP__TRP__SHIFT 0xf            # 4 bit

#define MC_SEQ_MISC_TIMING_LP__TRFC_MASK 0x1ff00000
#define MC_SEQ_MISC_TIMING_LP__TRFC__SHIFT 0x14          # 7 bit

# TCKE is not defined in gmc_8_1_sh_mask.h as a SEQ_MISC_TIMING

[Zorg33]

SEQ_RAS [2 2 14 14 2 42] right?

edited... think i messed up b4

TNOPW   1  
TNOPR   0
TR2W    21
TR2R    1  
TW2R   6  
TCL      19  

I parsed all the 32bit segments as the MC_SEQ_CAS_TIMING reference says but none of them has the values you mentioned.
Are these calculated with or without the value offsets (e.g CAS to read data return latency - 2).
So 19 is actually 19+2 or already with the offset 17+2? Neither seems good, it should be somewhere around 14.

By the way none of the 32bit segments seems plausible, I think there must be some other trick too.
Something with the order of the bits? (MSB-LSB?)

Too many combinations, I almost spent my whole day again on this.