Custom RAM Timings for GPU's with GDDR5 - DOWNLOAD LINKS - UPDATED

[xneoenx]

Can some one let me know if these values are right please?

2000 Hynix   
19   TRCDW
19   TRCDWA
27   TRCDR
27   TRCDRA
8   TRRD
83   TRC
0   TNOPW
0   TNOPR
24   TR2W
2   TCCDL
5   TR2R
21   TW2R
19   TCL
62   TRPWRA
15   TRPRDA
13   TRP
197   TRFC
 
Strap : BBB000000000000022889D0073EE8D53805515133ECF560C004E26017E0514206A8900A00200312 01C143840C5303F17

[1714607508]

1714607508

[1714607508]

1714607508

[1714607508]

1714607508

[1714607508]

1714607508

[1714607508]

1714607508

[1714607508]

1714607508

[Zorg33]

For the sake of scientific discovery collected 640+ bioses for R? [234]?? cards and written parser to extract timing table and related tables.
Here is the question.
Is there a proper way to determine size of timing table?

The segmentation of the timing straps differs for different series, so you have to use many different parsing rules to get the right numbers.
You have to gather all the required data.

[Metroid]

Couple of questions -
1- Are you Hex editing or using Polaris Bios Editor?  
2- How many watts are you pulling at the wall (no one cares about the 0.85v because it doesn't mean much)
3- What changes did you make to the latency, was it tRCD, tRCDW, tRC, tWTR .......etc?

Thanks

1 - Hex.
2- 5xrx480 = 670 watts from wall, measured with a device, psu EVGA 850G2, 240v, efficiency should be close to 92%.
3- I'm not going into specifics, I just loosed strict timings.

Hynix memory modules are much easier than Elpida concerning making a workable stable custom timings.

Well, the bottom line is, being limited by own choice at 0.85 memory and gpu core clock and yet trying to get the best of a product is challenging, in theory it might, testing shows a balance in execution.

Off topic: I returned from a long trip and looks like I received many private messages asking if I have roms for sale, I will say here the same thing I said to them, "I do not sell or distribute roms, my work is for scientific purposes, I hope you understand it.".

[zigun]

Can some one let me know if these values are right please?

2000 Hynix   
19   TRCDW
19   TRCDWA
27   TRCDR
27   TRCDRA
8   TRRD
83   TRC
0   TNOPW
0   TNOPR
24   TR2W
2   TCCDL
5   TR2R
21   TW2R
19   TCL
62   TRPWRA
15   TRPRDA
13   TRP
197   TRFC
 
Strap : BBB000000000000022889D0073EE8D53805515133ECF560C004E26017E0514206A8900A00200312 01C143840C5303F17

looks right

[niko2004x]

The segmentation of the timing straps differs for different series, so you have to use many different parsing rules to get the right numbers.
You have to gather all the required data.

Collected 1100+ bioses for R? [234]?? and HD [78]?? with GDDR5 and auto(nailed previous question already) extracted all timing tables (>90 unique variants excluding subsets and compositions).
It seems to me that RX and preRX should be segmented differently(and i know how) but for different preRX visible difference is few bits only (if any at all).

Edit: For example this is different values for 1250 strap for Elpida EDW2032BBBG from different cards ranging from HD 7730 to R9 380.

Code:

7771332000000000ad494930705509102d23e9030066e30022aa1c08640f2420ba8980a700000000130e1e2331242e11
7771332000000000ad495930705509102d15e9030068c30022aa1c08640f1420ba8980a700000000130e1e233e242e11
7771332000000000ad495930705509102d15e9030068c30022aa1c08640f1420ba8980a7000007c0130e1e233e242e11
7771332000000000ad495930705509102d23e9030066a30022aa1c08640f1420ba8980a7000007e0130e1e2331242e11
7771332000000000ad495930705509102d23e9030068c30022aa1c00640f1420ba8980a700000000130e1e2331242e11
7771332000000000ad495930705509102d23e9030068c30022aa1c00640f1420ba8980a7000007c0130e1e2331242e11
7771332000000000ad495930705509102d23e9030068c30022aa1c08640f1420ba8980a700000000130e1e2331242e11
7771332000000000ad495930705509102d23e9030068c30022aa1c08640f1420ba8980a700000000130e1e233e242e11
7771332000000000ad495930705509102d23e9030068c30022aa1c08640f1420ba8980a7000007c0130e1e2331242e11
7771332000000000ad495930705509102d23e9030068c30022aa1c08640f1420ba8980a7000007c0130e1e233e242e11
7771332000000000ad495930705509102d23e9030068c30022aa1c08640f1420ba8980a7000007e0130e1e2331242e11
7771332000000000ad497930705309102d23e9030066e30022aa1c00640f1420ba8980a700000000130e1e2331242e11
7771332000000000ad497930705309102d23e9030066e30022aa1c00640f1420ba8980a700000000130e1e2331242e11
7771332000000000ad497930705309102d23e9030066e30022aa1c00640f1420ba8980a700000000130e1e2331242e11
7771332000000000ad497930705309102d23e9030066e30022aa1c00640f1420ba8980a7000007c0130e1e2331242e11
7771332000000000ad497930705309102d23e9030066e30022aa1c00640f1420ba8980a7000007c0130e1e2331242e11
7771332000000000ad497930705309102d23e9030066e30022aa1c00640f1420ba8980a7000007c0130e1e2331242e11
7771332000000000ad497930705309102d23e9030066e30022aa1c08640f1420ba8980a700000000130e1e2331242e11
7771332000000000ad497930705309102d23e9030066e30022aa1c08640f1420ba8980a700000000130e1e2331242e11
7771332000000000ad497930705309102d23e9030066e30022aa1c08640f1420ba8980a700000000130e1e2331242e11
7771332000000000ad497930705309102d23e9030066e30022aa1c08640f1420ba8980a700000200130e1e2331242e11
7771332000000000ad497930705309102d23e9030066e30022aa1c08640f1420ba8980a7000007c0130e1e2331242e11
7771332000000000ad497930705309102d23e9030066e30022aa1c08640f1420ba8980a7000007c0130e1e2331242e11
7771332000000000ad497930705309102d23e9030066e30022aa1c08640f1420ba8980a7000007c0130e1e2331242e11
7771332000000000ad497930705309102e23e9030066e30022aa1c0064001420ba8980a702000200130e1e2331242f11
7771332000000000ad497930705309102e23e9030066e30022aa1c0864001420ba8980a702000200130e1e2331242f11
7771332000000000ad497930705509102d23e9030066e30022aa1c00640f1420ba8980a700000000130e1e2331242e11
7771332000000000ad497930705509102d23e9030066e30022aa1c00640f1420ba8980a7000007c0130e1e2331242e11
7771332000000000ad497930705509102d23e9030066e30022aa1c08640f1420ba8980a700000000130e1e2331242e11
7771332000000000ad497930705509102d23e9030066e30022aa1c08640f1420ba8980a7000007c0130e1e2331242e11
7771332000000000ad497930705509102d23e9030066e30022aa1c08640f1420ba8980a7000007e0130e1e2331242e11

Edit: Pre HD 7??? timing tables look different from pre RX and RX tables.

Edit: It seems the proper way is to look not at card series but at bios version (AMD VERblalbla at the begining of the bios unless vendor messed it). Timing structure (at least for GDDR5) is the same for each of VER015.50 (RX series), VER015.(00-49) (R? [23], HD 7???, HD 8???), VER013 (middle/high-end HD 6???, some low-end HD 7???), VER012(low/middle-end HD 6???, all HD 5???). VER013 timing structure looks like VER015.(00-49) but located at different place (at least i do not know how to get offset difference). VER015.50 timing structure seems to be like VER015.(00-49) but with bits moved around.

[dallase]

Can some one let me know if these values are right please?

2000 Hynix   
19   TRCDW
19   TRCDWA
27   TRCDR
27   TRCDRA
8   TRRD
83   TRC
0   TNOPW
0   TNOPR
24   TR2W
2   TCCDL
5   TR2R
21   TW2R
19   TCL
62   TRPWRA
15   TRPRDA
13   TRP
197   TRFC
 
Strap : BBB000000000000022889D0073EE8D53805515133ECF560C004E26017E0514206A8900A00200312 01C143840C5303F17

looks right

Yup.

[moonmaths]

Maybe this is the wrong thread to jump in, but I was hoping someone could help me clarify something with ram timings.. My understanding is that they're the time allotted for the completion of a certain task done by the gpu.  If they are too large, your card will be sitting around doing nothing after it is done with the task.  Too little, and that obviously makes problems.   
I recently copy-pasted the straps from the 1500 to 1625 on my 480 Elpida's.  (Above that had all been copied from 1625).  These were my worst performers, going at 650h/s on xmr, but with the strap copy, they got to 710 with far fewer errors.  If the GPU is overclocked to 2000 Mhz anyway, why would this simple strap-copy have such an effect? 
More to the point: if you are clocked at 2000 Mhz (BIOS, in Polaris editor), why does fine-tuning the timing on all (or at least down to 1500) Mhz levels have an effect?  My simple mind is thrown off. 

[niko2004x]

For whose who wonder how timing segmentation for RX and preRX(HD7???, HD8???, R? 2??, R? 3??) differs here is some nice statistic of bitwise timing mean for different series/memtypes (0/1 - always 0/1, x - either 0 or 1) http://pastebin.com/vXt7TDcy.

[LoneRangir]

Would anyone be willing to help on this other thread on how to modify the voltage offset for RX 400s?  I'd like to make one of my W10 rigs into a linux rig, but I'd hate to give up my WattTool negative offsets.

I'm capable of doing hex editing, but I'm not sure which bit range of the rom image controls the offset.

https://bitcointalk.org/index.php?topic=1765111.0

Sorry to be a bit off topic, but you guys seem to know a thing or two.

[LoneRangir]

Would anyone be willing to help on this other thread on how to modify the voltage offset for RX 400s?  I'd like to make one of my W10 rigs into a linux rig, but I'd hate to give up my WattTool negative offsets.

I'm capable of doing hex editing, but I'm not sure which bit range of the rom image controls the offset.

https://bitcointalk.org/index.php?topic=1765111.0

Sorry to be a bit off topic, but you guys seem to know a thing or two.

https://bitcointalk.org/index.php?topic=1765111.msg17772700#msg17772700

Okay, thanks.  I see there will be a bit of a curve in order to get up to speed.  Do you know of a tutorial, or is there a script that parses the ROMs into sections, takes edits, and recalculates?

[niko2004x]

Ok. Compared Stilt and different sets of stock timings for Elpida EDW2032BBBG and Hynix H5GQ2H24AFR in preRX cards.
Relative to closest stock timings tables Stilt version essentialy edits TRC, TRRD and that's all.
Relative to majority of stock timings tables Stilt version additionally change one/two bytes in the upper half of timing string.
Somehow out of historical context i am not impressed.

[niko2004x]

If it's earlier than RAS, but it matters, it's probably PMG.

I think in preRX PMG is later than RAS, although it is earlier in RX. At least i am guessing it is PMG.
I am more interested about first and third 32bit words from the end of timing string.
First 32bit word from the end looks like set of four bytes with some Ts
(they are growing from strap to next strap in almost all cases).

[niko2004x]

If it's earlier than RAS, but it matters, it's probably PMG.

I think in preRX PMG is later than RAS, although it is earlier in RX. At least i am guessing it is PMG.
I am more interested about first and third 32bit words from the end of timing string.
First 32bit word from the end looks like set of four bytes with some Ts
(they are growing from strap to next strap in almost all cases).

It's PMG. Oh, first and third? That would be your ARB_DRAM_TIMING2 and your MISC_TIMING2, IIRC.

As for ARB_DRAM_TIMING2 i though so too.
ARB_DRAM_TIMING and ARB_DRAM_TIMING2 are the only *_TIMING* defs from relevant parts of linux kernel which fit here datawise.
As for MISC_TIMING2 i am not so sure.
Datawise (padding bits, segmentation statistics etc) I thougt that MISC_TIMING2 comes right after MISC_TIMING (at lest it fits here better).

Edit: if last one really ARB_DRAM_TIMING2 then Stilt mostly reduces RAS2RAS (the biggest one) here.

Edit: Since it is unclear if RAS2RAS was initially reduced by vendors or by Stilt i compared RAS2RAS in
different RX and preRX bioses with Hynix H5GC4H24AJR and Elpida EDW4032BABG (no Stilt timings here as far as i know).
For preRX there are bioses with relatively large and relatively small values of RAS2RAS for each strap.
For RX only large.

[dallase]

If it's earlier than RAS, but it matters, it's probably PMG.

I think in preRX PMG is later than RAS, although it is earlier in RX. At least i am guessing it is PMG.
I am more interested about first and third 32bit words from the end of timing string.
First 32bit word from the end looks like set of four bytes with some Ts
(they are growing from strap to next strap in almost all cases).

It's PMG. Oh, first and third? That would be your ARB_DRAM_TIMING2 and your MISC_TIMING2, IIRC.

As for ARB_DRAM_TIMING2 i though so too.
ARB_DRAM_TIMING and ARB_DRAM_TIMING2 are the only *_TIMING* defs from relevant parts of linux kernel which fit here datawise.
As for MISC_TIMING2 i am not so sure.
Datawise (padding bits, segmentation statistics etc) I thougt that MISC_TIMING2 comes right after MISC_TIMING (at lest it fits here better).

Edit: if last one really ARB_DRAM_TIMING2 then Stilt mostly reduces RAS2RAS (the biggest one) here.

Edit: Since it is unclear if RAS2RAS was initially reduced by vendors or by Stilt i compared RAS2RAS in
different RX and preRX bioses with Hynix H5GC4H24AJR and Elpida EDW4032BABG (no Stilt timings here as far as i know).
For preRX there are bioses with relatively large and relatively small values of RAS2RAS for each strap.
For RX only large.

I have MISC2 in register 6.

Code:

----------------------------------------------------------------------------------------------------
Strap (RAS)                   trc    trcdr   trcdra    trcdw   trcdwa     trrd 
----------------------------------------------------------------------------------------------------
MSI-470-Hynix-Stock-1375       57       19       19       14       14        5 
MSI-470-Hynix-Stock-1425       59       20       20       14       14        6 
MSI-470-Hynix-Stock-1500       61       20       20       14       14        6 
MSI-470-Hynix-Stock-1625       68       23       23       16       16        7 
MSI-470-Hynix-Stock-1750       72       24       24       17       17        7 
MSI-470-Hynix-Stock-2000       83       27       27       19       19        8 
----------------------------------------------------------------------------------------------------
Strap (CAS)                 tccdl      tcl    tnopr    tnopw     tr2r     tr2w     tw2r 
----------------------------------------------------------------------------------------------------
MSI-470-Hynix-Stock-1375        2       17        0        0        5       24       17 
MSI-470-Hynix-Stock-1425        2       17        0        0        5       24       17 
MSI-470-Hynix-Stock-1500        2       18        0        0        5       25       17 
MSI-470-Hynix-Stock-1625        2       18        0        0        5       24       19 
MSI-470-Hynix-Stock-1750        2       19        0        0        5       25       19 
MSI-470-Hynix-Stock-2000        2       19        0        0        5       24       21 
----------------------------------------------------------------------------------------------------
Strap (MISC)                 trfc      trp   trprda   trpwra 
----------------------------------------------------------------------------------------------------
MSI-470-Hynix-Stock-1375      136        9       10       46 
MSI-470-Hynix-Stock-1425      141        9       11       47 
MSI-470-Hynix-Stock-1500      148        9       11       48 
MSI-470-Hynix-Stock-1625      164       11       12       55 
MSI-470-Hynix-Stock-1750      173       11       13       57 
MSI-470-Hynix-Stock-2000      197       13       15       62 
----------------------------------------------------------------------------------------------------
Strap (MISC2)                 faw pa2rdata pa2wdata    t32aw    tredc twdatatr    twedc 
----------------------------------------------------------------------------------------------------
MSI-470-Hynix-Stock-1375        8        0        0        6        2        0        6 
MSI-470-Hynix-Stock-1425       10        0        0        7        2        0        6 
MSI-470-Hynix-Stock-1500       10        0        0        7        2        0        6 
MSI-470-Hynix-Stock-1625       12        0        0        8        2        0        6 
MSI-470-Hynix-Stock-1750       12        0        0        8        2        0        6 
MSI-470-Hynix-Stock-2000       14        0        0        9        2        0        6 
----------------------------------------------------------------------------------------------------

[niko2004x]

I have MISC2 in register 6.

Code:

----------------------------------------------------------------------------------------------------
Strap (RAS)                   trc    trcdr   trcdra    trcdw   trcdwa     trrd 
----------------------------------------------------------------------------------------------------
MSI-470-Hynix-Stock-1375       57       19       19       14       14        5 
MSI-470-Hynix-Stock-1425       59       20       20       14       14        6 
MSI-470-Hynix-Stock-1500       61       20       20       14       14        6 
MSI-470-Hynix-Stock-1625       68       23       23       16       16        7 
MSI-470-Hynix-Stock-1750       72       24       24       17       17        7 
MSI-470-Hynix-Stock-2000       83       27       27       19       19        8 
----------------------------------------------------------------------------------------------------
Strap (CAS)                 tccdl      tcl    tnopr    tnopw     tr2r     tr2w     tw2r 
----------------------------------------------------------------------------------------------------
MSI-470-Hynix-Stock-1375        2       17        0        0        5       24       17 
MSI-470-Hynix-Stock-1425        2       17        0        0        5       24       17 
MSI-470-Hynix-Stock-1500        2       18        0        0        5       25       17 
MSI-470-Hynix-Stock-1625        2       18        0        0        5       24       19 
MSI-470-Hynix-Stock-1750        2       19        0        0        5       25       19 
MSI-470-Hynix-Stock-2000        2       19        0        0        5       24       21 
----------------------------------------------------------------------------------------------------
Strap (MISC)                 trfc      trp   trprda   trpwra 
----------------------------------------------------------------------------------------------------
MSI-470-Hynix-Stock-1375      136        9       10       46 
MSI-470-Hynix-Stock-1425      141        9       11       47 
MSI-470-Hynix-Stock-1500      148        9       11       48 
MSI-470-Hynix-Stock-1625      164       11       12       55 
MSI-470-Hynix-Stock-1750      173       11       13       57 
MSI-470-Hynix-Stock-2000      197       13       15       62 
----------------------------------------------------------------------------------------------------
Strap (MISC2)                 faw pa2rdata pa2wdata    t32aw    tredc twdatatr    twedc 
----------------------------------------------------------------------------------------------------
MSI-470-Hynix-Stock-1375        8        0        0        6        2        0        6 
MSI-470-Hynix-Stock-1425       10        0        0        7        2        0        6 
MSI-470-Hynix-Stock-1500       10        0        0        7        2        0        6 
MSI-470-Hynix-Stock-1625       12        0        0        8        2        0        6 
MSI-470-Hynix-Stock-1750       12        0        0        8        2        0        6 
MSI-470-Hynix-Stock-2000       14        0        0        9        2        0        6 
----------------------------------------------------------------------------------------------------

I think that used decoding scheme for MISC is wrong for RX (it produces data in unused bits) but correct if used for preRX.
At least for Hynix H5GC4H24AJR (too lazy to check Elpida EDW4032BABG) it seems different MISC decoders for RX and preRX should be used
to produce same values for MISC Ts.

[niko2004x]

Is there a way to read GPU memory error counter in linux?
In windows it seems hwinfo does it somehome.
Something on i2c bus perhaps?

[kilo17]

Seems I have missed a bunch of good stuff the last week or 2.  I have been traveling a bit.

[niko2004x]

dmesg usually tells you, at least if you fuck up bad.

Well i already written cli util to do arbitrary edits of timings table like

Code:

python atom_timings_editor.py -i original.rom -o patched.rom -r -p 0:150000+=0:150000[TRC=55,TRDD=5,RAS2RAS=150]

and atiflash we already have.
So i was hoping to get some 'soft' signal in addition to miner perfomance to auto optimize.
When dmesg tells it is already too bad imo.

[ray_saeed]

I am interested in purchasing custom Elpida and Samsung roms for XMR mining with  Nitro+ RX 470 OC cards (4GB and 8GB). If you have stable custom roms available please message me with a quote. Thanks.

[EuroCanuck]

I am interested in purchasing custom Elpida and Samsung roms for XMR mining with  Nitro+ RX 470 OC cards (4GB and 8GB). If you have stable custom roms available please message me with a quote. Thanks.

dude,for free i will help you out.im mining with xfx rx470 4gb black's with elpida. all 24 at doing 28.3mhs on eth and 110ish watts each.