niko2004x
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March 06, 2017, 12:25:30 AM Last edit: March 06, 2017, 02:31:31 AM by niko2004x |
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Interesting to know that there are others out there (who seemingly popped out of no where) with some decent knowledge.
I do not think it is 'out of no where'. This thread contains all knowledge which is necessary to contruct encoder/decoder for most registers in timing string.
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quocthanh1302
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March 06, 2017, 09:22:37 AM |
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MC_SEQ_RAS_TIMING - RW - 32 bits - MCIND:0x61 TRCDW 4:0 5bit Number of cycles from active to write TRCDWA 9:5 5bit Number of cycles from active to write with auto-precharge TRCDR 14:10 5bit Number of cycles from active to read TRCDRA 19:15 5bit Number of cycles from active to read with auto-precharge TRRD 23:20 4bit Number of cycles from active bank a to active bank b TRC 30:24 7bit Number of cycles from active to active/auto refresh
#define MC_SEQ_RAS_TIMING_LP__TRCDW_MASK 0x1f #define MC_SEQ_RAS_TIMING_LP__TRCDW__SHIFT 0x0 5 bits
#define MC_SEQ_RAS_TIMING_LP__TRCDWA_MASK 0x3e0 #define MC_SEQ_RAS_TIMING_LP__TRCDWA__SHIFT 0x5 5 bits
#define MC_SEQ_RAS_TIMING_LP__TRCDR_MASK 0x7c00 #define MC_SEQ_RAS_TIMING_LP__TRCDR__SHIFT 0xa 5 bits
#define MC_SEQ_RAS_TIMING_LP__TRCDRA_MASK 0xf8000 #define MC_SEQ_RAS_TIMING_LP__TRCDRA__SHIFT 0xf 5 bits
#define MC_SEQ_RAS_TIMING_LP__TRRD_MASK 0xf00000 #define MC_SEQ_RAS_TIMING_LP__TRRD__SHIFT 0x14 4 bits
#define MC_SEQ_RAS_TIMING_LP__TRC_MASK 0x7f000000 #define MC_SEQ_RAS_TIMING_LP__TRC__SHIFT 0x18 7 bits
MC_SEQ_CAS_TIMING - RW - 32 bits - MCIND:0x62 TNOPW 1:0 2bit Extra cycle(s) between successive write bursts TNOPR 3:2 2bit Extra cycle(s) between successive read bursts TR2W 8:4 5bit Read to write turn TCCDL 11:9 3bit Cycles between r/w from bank A to r/w bank B. TR2R 15:12 4bit Read to read time TW2R 20:16 5bit Write to read turn ---- 23:21 3bit Unused. TCL 28:24 5bit CAS to data return latency
#define MC_SEQ_CAS_TIMING_LP__TNOPW_MASK 0x3 #define MC_SEQ_CAS_TIMING_LP__TNOPW__SHIFT 0x0 # 2 bit
#define MC_SEQ_CAS_TIMING_LP__TNOPR_MASK 0xc #define MC_SEQ_CAS_TIMING_LP__TNOPR__SHIFT 0x2 # 2 bit
#define MC_SEQ_CAS_TIMING_LP__TR2W_MASK 0x1f0 #define MC_SEQ_CAS_TIMING_LP__TR2W__SHIFT 0x4 # 5 bit
#define MC_SEQ_CAS_TIMING_LP__TCCDL_MASK 0xe00 #define MC_SEQ_CAS_TIMING_LP__TCCDL__SHIFT 0x9 # 3 bit
#define MC_SEQ_CAS_TIMING_LP__TR2R_MASK 0xf000 # 4 bit #define MC_SEQ_CAS_TIMING_LP__TR2R__SHIFT 0xc
#define MC_SEQ_CAS_TIMING_LP__TW2R_MASK 0x1f0000 # 5 bit #define MC_SEQ_CAS_TIMING_LP__TW2R__SHIFT 0x10
#define MC_SEQ_CAS_TIMING_LP__TCL_MASK 0x1f000000 # 5 bit #define MC_SEQ_CAS_TIMING_LP__TCL__SHIFT 0x18
MC_SEQ_MISC_TIMING - RW - 32 bits - MCIND:0x63
TRP_WRA 5:0 6bit From write with auto-precharge to active - 1. ---- 7:6 2bit Unused TRP_RDA 13:8 6bit From read with auto-precharge to active - 1. ---- 16:14 3bit Unused TRP 19:16 4bit Precharge command period - 1. TRFC 26:20 7bit Auto-refresh command period - 1. TCKE 31:28 4bit CKE power down exit timer.
#define MC_SEQ_MISC_TIMING_LP__TRP_WRA_MASK 0x3f #define MC_SEQ_MISC_TIMING_LP__TRP_WRA__SHIFT 0x0 # 6 bit #define MC_SEQ_MISC_TIMING_LP__TRP_RDA_MASK 0x3f00 #define MC_SEQ_MISC_TIMING_LP__TRP_RDA__SHIFT 0x8 # 6 bit
#define MC_SEQ_MISC_TIMING_LP__TRP_MASK 0xf8000 #define MC_SEQ_MISC_TIMING_LP__TRP__SHIFT 0xf # 4 bit
#define MC_SEQ_MISC_TIMING_LP__TRFC_MASK 0x1ff00000 #define MC_SEQ_MISC_TIMING_LP__TRFC__SHIFT 0x14 # 7 bit
# TCKE is not defined in gmc_8_1_sh_mask.h as a SEQ_MISC_TIMING
can you show structure MISC2 in bits like RAS CAS MISC above, thanks.
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laik2
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March 06, 2017, 11:08:20 AM |
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MC_SEQ_RAS_TIMING - RW - 32 bits - MCIND:0x61 TRCDW 4:0 5bit Number of cycles from active to write TRCDWA 9:5 5bit Number of cycles from active to write with auto-precharge TRCDR 14:10 5bit Number of cycles from active to read TRCDRA 19:15 5bit Number of cycles from active to read with auto-precharge TRRD 23:20 4bit Number of cycles from active bank a to active bank b TRC 30:24 7bit Number of cycles from active to active/auto refresh
#define MC_SEQ_RAS_TIMING_LP__TRCDW_MASK 0x1f #define MC_SEQ_RAS_TIMING_LP__TRCDW__SHIFT 0x0 5 bits
#define MC_SEQ_RAS_TIMING_LP__TRCDWA_MASK 0x3e0 #define MC_SEQ_RAS_TIMING_LP__TRCDWA__SHIFT 0x5 5 bits
#define MC_SEQ_RAS_TIMING_LP__TRCDR_MASK 0x7c00 #define MC_SEQ_RAS_TIMING_LP__TRCDR__SHIFT 0xa 5 bits
#define MC_SEQ_RAS_TIMING_LP__TRCDRA_MASK 0xf8000 #define MC_SEQ_RAS_TIMING_LP__TRCDRA__SHIFT 0xf 5 bits
#define MC_SEQ_RAS_TIMING_LP__TRRD_MASK 0xf00000 #define MC_SEQ_RAS_TIMING_LP__TRRD__SHIFT 0x14 4 bits
#define MC_SEQ_RAS_TIMING_LP__TRC_MASK 0x7f000000 #define MC_SEQ_RAS_TIMING_LP__TRC__SHIFT 0x18 7 bits
MC_SEQ_CAS_TIMING - RW - 32 bits - MCIND:0x62 TNOPW 1:0 2bit Extra cycle(s) between successive write bursts TNOPR 3:2 2bit Extra cycle(s) between successive read bursts TR2W 8:4 5bit Read to write turn TCCDL 11:9 3bit Cycles between r/w from bank A to r/w bank B. TR2R 15:12 4bit Read to read time TW2R 20:16 5bit Write to read turn ---- 23:21 3bit Unused. TCL 28:24 5bit CAS to data return latency
#define MC_SEQ_CAS_TIMING_LP__TNOPW_MASK 0x3 #define MC_SEQ_CAS_TIMING_LP__TNOPW__SHIFT 0x0 # 2 bit
#define MC_SEQ_CAS_TIMING_LP__TNOPR_MASK 0xc #define MC_SEQ_CAS_TIMING_LP__TNOPR__SHIFT 0x2 # 2 bit
#define MC_SEQ_CAS_TIMING_LP__TR2W_MASK 0x1f0 #define MC_SEQ_CAS_TIMING_LP__TR2W__SHIFT 0x4 # 5 bit
#define MC_SEQ_CAS_TIMING_LP__TCCDL_MASK 0xe00 #define MC_SEQ_CAS_TIMING_LP__TCCDL__SHIFT 0x9 # 3 bit
#define MC_SEQ_CAS_TIMING_LP__TR2R_MASK 0xf000 # 4 bit #define MC_SEQ_CAS_TIMING_LP__TR2R__SHIFT 0xc
#define MC_SEQ_CAS_TIMING_LP__TW2R_MASK 0x1f0000 # 5 bit #define MC_SEQ_CAS_TIMING_LP__TW2R__SHIFT 0x10
#define MC_SEQ_CAS_TIMING_LP__TCL_MASK 0x1f000000 # 5 bit #define MC_SEQ_CAS_TIMING_LP__TCL__SHIFT 0x18
MC_SEQ_MISC_TIMING - RW - 32 bits - MCIND:0x63
TRP_WRA 5:0 6bit From write with auto-precharge to active - 1. ---- 7:6 2bit Unused TRP_RDA 13:8 6bit From read with auto-precharge to active - 1. ---- 16:14 3bit Unused TRP 19:16 4bit Precharge command period - 1. TRFC 26:20 7bit Auto-refresh command period - 1. TCKE 31:28 4bit CKE power down exit timer.
#define MC_SEQ_MISC_TIMING_LP__TRP_WRA_MASK 0x3f #define MC_SEQ_MISC_TIMING_LP__TRP_WRA__SHIFT 0x0 # 6 bit #define MC_SEQ_MISC_TIMING_LP__TRP_RDA_MASK 0x3f00 #define MC_SEQ_MISC_TIMING_LP__TRP_RDA__SHIFT 0x8 # 6 bit
#define MC_SEQ_MISC_TIMING_LP__TRP_MASK 0xf8000 #define MC_SEQ_MISC_TIMING_LP__TRP__SHIFT 0xf # 4 bit
#define MC_SEQ_MISC_TIMING_LP__TRFC_MASK 0x1ff00000 #define MC_SEQ_MISC_TIMING_LP__TRFC__SHIFT 0x14 # 7 bit
# TCKE is not defined in gmc_8_1_sh_mask.h as a SEQ_MISC_TIMING
can you show structure MISC2 in bits like RAS CAS MISC above, thanks. THere is no TCKE in MC_SEQ_MISC_TIMING for GDDR5 I was doing it all wrong before I noticed that myself
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dallase
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March 06, 2017, 02:52:35 PM |
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MC_SEQ_RAS_TIMING - RW - 32 bits - MCIND:0x61 TRCDW 4:0 5bit Number of cycles from active to write TRCDWA 9:5 5bit Number of cycles from active to write with auto-precharge TRCDR 14:10 5bit Number of cycles from active to read TRCDRA 19:15 5bit Number of cycles from active to read with auto-precharge TRRD 23:20 4bit Number of cycles from active bank a to active bank b TRC 30:24 7bit Number of cycles from active to active/auto refresh
#define MC_SEQ_RAS_TIMING_LP__TRCDW_MASK 0x1f #define MC_SEQ_RAS_TIMING_LP__TRCDW__SHIFT 0x0 5 bits
#define MC_SEQ_RAS_TIMING_LP__TRCDWA_MASK 0x3e0 #define MC_SEQ_RAS_TIMING_LP__TRCDWA__SHIFT 0x5 5 bits
#define MC_SEQ_RAS_TIMING_LP__TRCDR_MASK 0x7c00 #define MC_SEQ_RAS_TIMING_LP__TRCDR__SHIFT 0xa 5 bits
#define MC_SEQ_RAS_TIMING_LP__TRCDRA_MASK 0xf8000 #define MC_SEQ_RAS_TIMING_LP__TRCDRA__SHIFT 0xf 5 bits
#define MC_SEQ_RAS_TIMING_LP__TRRD_MASK 0xf00000 #define MC_SEQ_RAS_TIMING_LP__TRRD__SHIFT 0x14 4 bits
#define MC_SEQ_RAS_TIMING_LP__TRC_MASK 0x7f000000 #define MC_SEQ_RAS_TIMING_LP__TRC__SHIFT 0x18 7 bits
MC_SEQ_CAS_TIMING - RW - 32 bits - MCIND:0x62 TNOPW 1:0 2bit Extra cycle(s) between successive write bursts TNOPR 3:2 2bit Extra cycle(s) between successive read bursts TR2W 8:4 5bit Read to write turn TCCDL 11:9 3bit Cycles between r/w from bank A to r/w bank B. TR2R 15:12 4bit Read to read time TW2R 20:16 5bit Write to read turn ---- 23:21 3bit Unused. TCL 28:24 5bit CAS to data return latency
#define MC_SEQ_CAS_TIMING_LP__TNOPW_MASK 0x3 #define MC_SEQ_CAS_TIMING_LP__TNOPW__SHIFT 0x0 # 2 bit
#define MC_SEQ_CAS_TIMING_LP__TNOPR_MASK 0xc #define MC_SEQ_CAS_TIMING_LP__TNOPR__SHIFT 0x2 # 2 bit
#define MC_SEQ_CAS_TIMING_LP__TR2W_MASK 0x1f0 #define MC_SEQ_CAS_TIMING_LP__TR2W__SHIFT 0x4 # 5 bit
#define MC_SEQ_CAS_TIMING_LP__TCCDL_MASK 0xe00 #define MC_SEQ_CAS_TIMING_LP__TCCDL__SHIFT 0x9 # 3 bit
#define MC_SEQ_CAS_TIMING_LP__TR2R_MASK 0xf000 # 4 bit #define MC_SEQ_CAS_TIMING_LP__TR2R__SHIFT 0xc
#define MC_SEQ_CAS_TIMING_LP__TW2R_MASK 0x1f0000 # 5 bit #define MC_SEQ_CAS_TIMING_LP__TW2R__SHIFT 0x10
#define MC_SEQ_CAS_TIMING_LP__TCL_MASK 0x1f000000 # 5 bit #define MC_SEQ_CAS_TIMING_LP__TCL__SHIFT 0x18
MC_SEQ_MISC_TIMING - RW - 32 bits - MCIND:0x63
TRP_WRA 5:0 6bit From write with auto-precharge to active - 1. ---- 7:6 2bit Unused TRP_RDA 13:8 6bit From read with auto-precharge to active - 1. ---- 16:14 3bit Unused TRP 19:16 4bit Precharge command period - 1. TRFC 26:20 7bit Auto-refresh command period - 1. TCKE 31:28 4bit CKE power down exit timer.
#define MC_SEQ_MISC_TIMING_LP__TRP_WRA_MASK 0x3f #define MC_SEQ_MISC_TIMING_LP__TRP_WRA__SHIFT 0x0 # 6 bit #define MC_SEQ_MISC_TIMING_LP__TRP_RDA_MASK 0x3f00 #define MC_SEQ_MISC_TIMING_LP__TRP_RDA__SHIFT 0x8 # 6 bit
#define MC_SEQ_MISC_TIMING_LP__TRP_MASK 0xf8000 #define MC_SEQ_MISC_TIMING_LP__TRP__SHIFT 0xf # 4 bit
#define MC_SEQ_MISC_TIMING_LP__TRFC_MASK 0x1ff00000 #define MC_SEQ_MISC_TIMING_LP__TRFC__SHIFT 0x14 # 7 bit
# TCKE is not defined in gmc_8_1_sh_mask.h as a SEQ_MISC_TIMING
can you show structure MISC2 in bits like RAS CAS MISC above, thanks. THere is no TCKE in MC_SEQ_MISC_TIMING for GDDR5 I was doing it all wrong before I noticed that myself Ya, that was from the old M56 register specs. I'll try and consolidate all I have here.. RAS trcdw 4:0 5bit Number of cycles from active to write trcdwa 9:5 5bit Number of cycles from active to write with auto-precharge trcdr 14:10 5bit Number of cycles from active to read trcdra 19:15 5bit Number of cycles from active to read with auto-precharge trrd 23:20 4bit Number of cycles from active bank a to active bank b trc 30:24 7bit Number of cycles from active to active/auto refresh ---- 31 1bit Unused?
CAS tnopw 1:0 2bit Extra cycle(s) between successive write bursts tnopr 3:2 2bit Extra cycle(s) between successive read bursts tr2w 8:4 5bit Read to write turn tccdl 11:9 3bit Cycles between r/w from bank A to r/w bank B. tr2r 15:12 4bit Read to read time tw2r 20:16 5bit Write to read turn ---- 23:21 3bit Unused? tcl 28:24 5bit CAS to data return latency ---- 31:29 3bit Unused?
MISC trpwra 5:0 6bit From write with auto-precharge to active - 1. ---- 7:6 2bit Unused? trprda 13:8 6bit From read with auto-precharge to active - 1. ---- 15:14 2bit Unused? trp 19:16 4bit Precharge command period - 1. trfc 26:20 9bit Auto-refresh command period - 1. ---- 27 3bit Unused?
MISC2 pa2rdata 3:0 4bit pa2wdata 7:4 4bit faw 12:8 5bit 4 activate windows tredc 15:13 3bit twedc 20:16 5bit t32aw 28:21 8bit 32 activate windows twdatatr 31:29 3bit
PMG tcksre 3:0 4bit tcksrx 7:4 4bit tcke_pulse 11:8 4bit tcke 18:12 7bit seq_idle 22:19 4bit tcke_pulse_msb 23 1bit seq_idle_ss 24 1bit
ARB actrd 7:0 8bit actwr 15:8 8bit rasmactrd 23:16 8bit rasmactwr 31:24 8bit
ARB2 ras2ras 7:0 8bit rp 15:8 8bit wrplusrp 23:16 8bit bus_turn 31:24 8bit
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dallase
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March 06, 2017, 02:53:41 PM |
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can you show structure MISC2 in bits like RAS CAS MISC above, thanks.
see my previous post.
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madLyfe
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March 07, 2017, 04:27:24 AM |
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Evilop;
some love for my ref MSI RX480 4gb hynix please?
1500: 777000000000000022339D00CE516A3D9055111230CB4409004AE600740114206A8900A00200312 0150F292F94273116 777000000000000022339D00CE5153379055111230CB440900208400740114206A8900A00200312 0150F292F94273116 1625: 999000000000000022559D0010DE7B4480551312B78C450A004C0601750414206A8900A00200312 018112D34A42A3816 1750: 999000000000000022559D0031627C489055131339CDD50A004C06017D0514206A8900A00200312 019123037AD2C3A17 2000: BBB000000000000022889D0073EE8D53805515133ECF560C004E26017E0514206A8900A00200312 01C143840C5303F17
Thank you..
Small change (just so you know, i'm not going to do this on a daily base.. :p) Greetings! Thank you Eliovp. Try it not stable for me, but after change it from 79 to 98 it got stable with same speed. 777000000000000022339D00CE51533 98055111230CB440900208400740114206A8900A002003120150F292F94273116 Maybe cause my card not good enough, or cause I still playing game with my pc. would i be able to use these timings on my two asus rog strix oc rx470 hynix 4gb? i have copied the 1500 timings to all the higher values and flashed that. if i try to OC the cards mem to 2000 using afterburner or wattman i cant seem to keep it stable. im running win 7 64bit.
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bughatti
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March 07, 2017, 04:34:17 AM |
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840W ATW 6x Sapphire Nitro+ RX 480 { "gpu_temp": " 61 61 61 62 61 60", "gpu_fanspeed": " 45 40 40 27 29 20", "gpu_core": " 1150 1150 1150 1150 1150 1150 ", "gpu_memory": " 2125 2125 2125 2125 2125 2125 " } Is this the rx480 4gb or 8gb and also what memory. I have the sapphire nitro+ rx 480 4gb elpida. I currently run anorak's OC rom and can get 28.1 per card but thats it.
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duole
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March 07, 2017, 05:54:24 AM |
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840W ATW 6x Sapphire Nitro+ RX 480 http://i63.tinypic.com/6rmxxu.png{ "gpu_temp": " 61 61 61 62 61 60", "gpu_fanspeed": " 45 40 40 27 29 20", "gpu_core": " 1150 1150 1150 1150 1150 1150 ", "gpu_memory": " 2125 2125 2125 2125 2125 2125 " } Is this the rx480 4gb or 8gb and also what memory. I have the sapphire nitro+ rx 480 4gb elpida. I currently run anorak's OC rom and can get 28.1 per card but thats it. this's Samsung bro
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nerdralph
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March 07, 2017, 04:06:28 PM |
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I got my 2 Sapphire 470 Nitro+ 4GB with Samsung rock solid @ 29.5MH/s on eth.
This is on Linux box... Maybe win would be a bit faster.
I got 30+ but it's not that stable...
Can you post the strap you are using? I'm not having much luck getting my Sapphire 470 over 27Mh. That's running memory at 1900 with the 1500 strap. Using the 1375 strap gives me errors mining ZEC. Here's the 1375 & 1500 straps from the stock BIOS: 333000000000000022CC1C008CCD593AC0570D13AA09B4070048C7007A0014207A8900A002000000140D272E7B252B15 555000000000000022CC1C00AD515A3EC0570E142D4A64080048C700030114207A8900A003000000150E2A3186272E16
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fury420
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March 07, 2017, 06:16:41 PM Last edit: March 11, 2017, 05:58:18 PM by fury420 |
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I got my 2 Sapphire 470 Nitro+ 4GB with Samsung rock solid @ 29.5MH/s on eth.
This is on Linux box... Maybe win would be a bit faster.
I got 30+ but it's not that stable...
Can you post the strap you are using? I'm not having much luck getting my Sapphire 470 over 27Mh. That's running memory at 1900 with the 1500 strap. Using the 1375 strap gives me errors mining ZEC. Here's the 1375 & 1500 straps from the stock BIOS: 333000000000000022CC1C008CCD593AC0570D13AA09B4070048C7007A0014207A8900A002000000140D272E7B252B15 555000000000000022CC1C00AD515A3EC0570E142D4A64080048C700030114207A8900A003000000150E2A3186272E16
My best results with Samsung 4GB ( K4G41325FE ) have been using the 1625mhz strap at 1950-2050mhz but I'm still trying to determine long-term stability for each individual card stock 1625mhz strap: 555000000000000022CC1C00CE596B44D0570F1531CB2409004AE7000B0314207A8900A003000000170F2E36922A3217
1150 / 2000mhz = 28.1mh (MSI 470 Gaming 4GB) 1150 / 1900mhz = 27.5mh (MSI 470 Armor 4GB) Using Claymore in Windows, 16.11.5 drivers I've noticed some odd behavior though... on my initial attempt I was able to gradually raise clocks on one card as high as ~2100mhz (I saw 29.5mh!), but it only seems to work if I raise the clocks while miner is already running and then pause/unpause, the initial miner / DAG loading does not seem stable with these timings at high clocks. My other test card I seemingly had mining stable up to 2050mhz, only to find that it can't create the DAG at anything above 1965mhz without crashing the system I've also noticed that the Samsung 4GB equipped cards doesn't seem to report any GPU memory errors in Hwinfo64, even when memory clocks are pushed high enough to cause errors / crashes in Claymore.
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laik2
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March 07, 2017, 07:47:11 PM Last edit: March 09, 2017, 07:54:59 AM by laik2 |
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Each card is different. I got 2 identical GPUs with 8G samsung memory and 1342 stock core I believe Sapphire Nitro+ 480 OC is the right model. One of them did 32.5 with Claymore at 1200/2225 and was stable without errors, the other crashes after a minute on 2100 clock... so test each card individually.
PP: As it is already said dagger-hashimoto performs better with loosened timings and higher memory clock. Don't expect miracles on clocks below 2000.
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lpedretti
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March 09, 2017, 02:13:37 AM |
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I want to jump on editing the straps, so far i have a general idea of what each of the values mean and i'll use the cheatsheet at http://www.tweakers.fr/timings.html#tRP once i can get to edit them, but i'm not sure on how to get the info for my specific memory to know where is each of the memory timings. Where should i start? Thanx guys! Best regards
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AC: ANuRoFPkCjZSxsw2S41djrrA1D4xMMmwhs
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laik2
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March 09, 2017, 09:01:42 AM |
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I got my 2 Sapphire 470 Nitro+ 4GB with Samsung rock solid @ 29.5MH/s on eth.
This is on Linux box... Maybe win would be a bit faster.
I got 30+ but it's not that stable...
Can you post the strap you are using? I'm not having much luck getting my Sapphire 470 over 27Mh. That's running memory at 1900 with the 1500 strap. Using the 1375 strap gives me errors mining ZEC. Here's the 1375 & 1500 straps from the stock BIOS: 333000000000000022CC1C008CCD593AC0570D13AA09B4070048C7007A0014207A8900A002000000140D272E7B252B15 555000000000000022CC1C00AD515A3EC0570E142D4A64080048C700030114207A8900A003000000150E2A3186272E16
Use 1625 Timing it's much better for ethereum.
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NisamRobot
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March 10, 2017, 06:55:58 AM |
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Hello, can someone please tell me if these values are correct?
----PMG---- TCKSRE = 2 TCKSRX = 2 TCKE_PLS = 3 TCKE = 83 SEQ_IDLE = 3 TCKE_PLS_M = 1 SEQ_IDLE_SS= 0
----ARB1---- ACTRD = 21 ACTWR = 15 RASMACTRD= 41 RASMACTWD= 47
----ARB2---- RAS2RAS = 148 RP = 39 WRPLUSRP = 49 BUS_TURN = 22
hynix 1500 strap 777000000000000022339D00CE516A3D9055111230CB4409004AE600740114206A8900A00200312 0150F292F94273116
Thx!
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ParkExcite
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March 10, 2017, 07:44:23 AM |
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840W ATW 6x Sapphire Nitro+ RX 480 { "gpu_temp": " 61 61 61 62 61 60", "gpu_fanspeed": " 45 40 40 27 29 20", "gpu_core": " 1150 1150 1150 1150 1150 1150 ", "gpu_memory": " 2125 2125 2125 2125 2125 2125 " } Really nice, currently i'm at 800W ATW with 4 RX 470 and a R9 290 for 140Mh
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laik2
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March 10, 2017, 09:18:31 AM |
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Hello, can someone please tell me if these values are correct?
----PMG---- TCKSRE = 2 TCKSRX = 2 TCKE_PLS = 3 TCKE = 83 SEQ_IDLE = 3 TCKE_PLS_M = 1 SEQ_IDLE_SS= 0
----ARB1---- ACTRD = 21 ACTWR = 15 RASMACTRD= 41 RASMACTWD= 47
----ARB2---- RAS2RAS = 148 RP = 39 WRPLUSRP = 49 BUS_TURN = 22
hynix 1500 strap 777000000000000022339D00CE516A3D9055111230CB4409004AE600740114206A8900A00200312 0150F292F94273116
Thx!
TCKSRE = 2, TCKSRX = 2, TCKE_PULSE = 3, TCKE = 19, SEQ_IDLE = 7, TCKE_PULSE_MSB = 0, SEQ_IDLE_SS = 0 By my calculations. Else is fine. EDIT: I wouldn't touch PMG timing
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kemo6600
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March 10, 2017, 09:45:28 AM |
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840W ATW 6x Sapphire Nitro+ RX 480
{ "gpu_temp": " 61 61 61 62 61 60", "gpu_fanspeed": " 45 40 40 27 29 20", "gpu_core": " 1150 1150 1150 1150 1150 1150 ", "gpu_memory": " 2125 2125 2125 2125 2125 2125 " }
Same clocks as you (Rejected shares from bad connection )
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laik2
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March 10, 2017, 02:24:58 PM |
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what VDDC offset? Try those on linux Also I didn't push the gpus too far, so they're a bit loosened..I'll post my best results on windows later.
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NisamRobot
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March 10, 2017, 03:54:15 PM |
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Hello, can someone please tell me if these values are correct?
----PMG---- TCKSRE = 2 TCKSRX = 2 TCKE_PLS = 3 TCKE = 83 SEQ_IDLE = 3 TCKE_PLS_M = 1 SEQ_IDLE_SS= 0
----ARB1---- ACTRD = 21 ACTWR = 15 RASMACTRD= 41 RASMACTWD= 47
----ARB2---- RAS2RAS = 148 RP = 39 WRPLUSRP = 49 BUS_TURN = 22
hynix 1500 strap 777000000000000022339D00CE516A3D9055111230CB4409004AE600740114206A8900A00200312 0150F292F94273116
Thx!
TCKSRE = 2, TCKSRX = 2, TCKE_PULSE = 3, TCKE = 19, SEQ_IDLE = 7, TCKE_PULSE_MSB = 0, SEQ_IDLE_SS = 0 By my calculations. Else is fine. EDIT: I wouldn't touch PMG timing Thank you! I won't touch PMG, not sure what is its purpose anyway. Not very experienced at this stuff. I'll just play with RAS, CAS, MISC.... brick my card maybe...
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kemo6600
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Activity: 130
Merit: 10
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March 10, 2017, 08:01:50 PM |
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what VDDC offset? Try those on linux Also I didn't push the gpus too far, so they're a bit loosened..I'll post my best results on windows later. -69V From Bios . pulling around 880W ATW from 6 cards .
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