Custom RAM Timings for GPU's with GDDR5 - DOWNLOAD LINKS - UPDATED

[nerdralph]

Are there any publicly available custom memory strap timings for the rx 400 series? (samsung, elpida, or hynix)

Here's the Samsung strap I'm currently working on:
777000000000000022CC1C0010625C49D0571016B50BD50900400700140514207A8900A00300000 0191131399D2C3617

It's the 1750 strap with RRD=5, FAW&32AW=0.  It's stable at 2100 on my Sapphire Rx470.  The previous custom strap I tried was based on the 1625 strap, and I would start getting a lot of errors over 2000.  I just started working on it today, so there's more tweaking to do (like trying a lower tRC for RAS).

[laik2]

Are there any publicly available custom memory strap timings for the rx 400 series? (samsung, elpida, or hynix)

Here's the Samsung strap I'm currently working on:
777000000000000022CC1C0010625C49D0571016B50BD50900400700140514207A8900A00300000 0191131399D2C3617

It's the 1750 strap with RRD=5, FAW&32AW=0.  It's stable at 2100 on my Sapphire Rx470.  The previous custom strap I tried was based on the 1625 strap, and I would start getting a lot of errors over 2000.  I just started working on it today, so there's more tweaking to do (like trying a lower tRC for RAS).

Nicely done
Lets see the final results.

Small adjustments to your timing based on my experience : 777000000000000022CC1C00CE615C45C0571016B30CD50900400700140514207A8900A00300000 0151031399D2C3617

[nerdralph]

Here's the Samsung strap I'm currently working on:
777000000000000022CC1C0010625C49D0571016B50BD50900400700140514207A8900A00300000 0191131399D2C3617

It's the 1750 strap with RRD=5, FAW&32AW=0.  It's stable at 2100 on my Sapphire Rx470.  The previous custom strap I tried was based on the 1625 strap, and I would start getting a lot of errors over 2000.  I just started working on it today, so there's more tweaking to do (like trying a lower tRC for RAS).

Nicely done
Lets see the final results.

Small adjustments to your timing based on my experience : 777000000000000022CC1C00CE615C45C0571016B30CD50900400700140514207A8900A00300000 0151031399D2C3617

You've got tRCDW(A) at 14 instead of 16, which shouldn't make any difference at all with ETH since it's all DAG reads. The tighter R2W and RP_WRA shouldn't make a difference for the same reason.  Looser timing for RP_RDA (12 vs 11) might help stability, but I'm not having any stability problems.  After 3 hrs of ETH mining at 28.3Mh, sgminer is showing just 45 HW errors.

update:
I tried tRC = 62 instead of 73, and got no speed increase (and then crash).  I tried RCDR(A)=22 instead of 24, and got no increase in speed but a big increase in errors.  So then I tried yours and I get a slight increase (~28.4 vs 28.3).

update2:
It looks like the performance increase comes from ARB_DRAM_TIMING.ACTRD.  You've got it at 21 vs 25 for my strap.

[nerdralph]

Here's the Samsung strap I'm currently working on:
777000000000000022CC1C0010625C49D0571016B50BD50900400700140514207A8900A00300000 0191131399D2C3617

It's the 1750 strap with RRD=5, FAW&32AW=0.  It's stable at 2100 on my Sapphire Rx470.  The previous custom strap I tried was based on the 1625 strap, and I would start getting a lot of errors over 2000.  I just started working on it today, so there's more tweaking to do (like trying a lower tRC for RAS).

Nicely done
Lets see the final results.

Small adjustments to your timing based on my experience : 777000000000000022CC1C00CE615C45C0571016B30CD50900400700140514207A8900A00300000 0151031399D2C3617

You've got tRCDW(A) at 14 instead of 16, which shouldn't make any difference at all with ETH since it's all DAG reads. The tighter R2W and RP_WRA shouldn't make a difference for the same reason.  Looser timing for RP_RDA (12 vs 11) might help stability, but I'm not having any stability problems.  After 3 hrs of ETH mining at 28.3Mh, sgminer is showing just 45 HW errors.

update:
I tried tRC = 62 instead of 73, and got no speed increase (and then crash).  I tried RCDR(A)=22 instead of 24, and got no increase in speed but a big increase in errors.  So then I tried yours and I get a slight increase (~28.4 vs 28.3).

update2:
It looks like the performance increase comes from ARB_DRAM_TIMING.ACTRD.  You've got it at 21 vs 25 for my strap.

Can anyone suggest any more improvements?  My Sapphire Rx470 seems to have a hard limit of 2100 for the memory clock.  Setting the memory clock to 2150 in the BIOS, and increasing Powerplay Max Mem Freq table from 2100 to 2150 shows the change in pp_dpm_mclk, but the hashrate doesn't change.  With the mclk set back to 2100, I dropped RAS2RAS from 157 to 150, but don't see any change in hashrate.

[lpedretti]

So I need to update MC_SEQ_MISC1, offset 54 in the hex string of the strap (offset 27 in bytes).  Are the 3 hex chars at offset 55-57 the 12 bits for MR0, or is that MR1 and MR0 is 59-61?
I know I could figure it out by comparing different straps and seeing how the bits map to the register values, but since you seem to have already figured it out...

Original Samsung 4G ( your particular GPU ) 1625
555000000000000022CC1C00CE596B44D0570F1531CB2409004AE700 [ 0B03 | 1420 ] 7A8900A003000000170F2E36922A3217

--> MC_SEQ_MISC1
 -- MR0
    WL = 3,  CL = 22,  TM = 0,  WR = 23,  BA0 = 0,  BA1 = 0,  BA2 = 0,  BA3 = 0
 -- MR1
    DS = 0,  DT = 1,  ADR = 1,  CAL = 0,  PLL = 0,  RDBI = 0,  WDBI = 0,  ABI = 0,
    RES = 0,  BA0 = 0,  BA1 = 1,  BA2 = 0,  BA3 = 0

Original Samsung 4G 1750
777000000000000022CC1C0010626C49D0571016B50BD509004AE700 [ 1405 | 1420 ] 7A8900A003000000191131399D2C3617

--> MC_SEQ_MISC1
 -- MR0
    WL = 4,  CL = 23,  TM = 0,  WR = 25,  BA0 = 0,  BA1 = 0,  BA2 = 0,  BA3 = 0
 -- MR1
    DS = 0,  DT = 1,  ADR = 1,  CAL = 0,  PLL = 0,  RDBI = 0,  WDBI = 0,  ABI = 0,
    RES = 0,  BA0 = 0,  BA1 = 1,  BA2 = 0,  BA3 = 0

I think you are off by +1 with the MR0 CAS latency.  SEQ_CAS_TIMING has CL=21(0x15) for the 1625 strap, and CL=22(0x16) for the 1750 strap.

Excuse my ignorance, but where is a 22 or 21 on 0x2014030B, or a 23 or 22 on 0x20140514 ?
22 binary is 10110, 21 binary is 10101, 23 binary is 10111, none of those patterns are in any of those two numbers... what am i missing?

[deadsix]

Seems like the samsung one doesn't have global offset.

Stock roms with global offset have either '03' +18.75mV value or '04' +25mV as VDDC offset.
I've never seen something else, or rather negative offset.. and i've opened up a lot of them ;-) 'But correct me if i'm wrong..'

Greetings.

Thank you Good sir.

[laik2]

So I need to update MC_SEQ_MISC1, offset 54 in the hex string of the strap (offset 27 in bytes).  Are the 3 hex chars at offset 55-57 the 12 bits for MR0, or is that MR1 and MR0 is 59-61?
I know I could figure it out by comparing different straps and seeing how the bits map to the register values, but since you seem to have already figured it out...

Original Samsung 4G ( your particular GPU ) 1625
555000000000000022CC1C00CE596B44D0570F1531CB2409004AE700 [ 0B03 | 1420 ] 7A8900A003000000170F2E36922A3217

--> MC_SEQ_MISC1
 -- MR0
    WL = 3,  CL = 22,  TM = 0,  WR = 23,  BA0 = 0,  BA1 = 0,  BA2 = 0,  BA3 = 0
 -- MR1
    DS = 0,  DT = 1,  ADR = 1,  CAL = 0,  PLL = 0,  RDBI = 0,  WDBI = 0,  ABI = 0,
    RES = 0,  BA0 = 0,  BA1 = 1,  BA2 = 0,  BA3 = 0

Original Samsung 4G 1750
777000000000000022CC1C0010626C49D0571016B50BD509004AE700 [ 1405 | 1420 ] 7A8900A003000000191131399D2C3617

--> MC_SEQ_MISC1
 -- MR0
    WL = 4,  CL = 23,  TM = 0,  WR = 25,  BA0 = 0,  BA1 = 0,  BA2 = 0,  BA3 = 0
 -- MR1
    DS = 0,  DT = 1,  ADR = 1,  CAL = 0,  PLL = 0,  RDBI = 0,  WDBI = 0,  ABI = 0,
    RES = 0,  BA0 = 0,  BA1 = 1,  BA2 = 0,  BA3 = 0

I think you are off by +1 with the MR0 CAS latency.  SEQ_CAS_TIMING has CL=21(0x15) for the 1625 strap, and CL=22(0x16) for the 1750 strap.

Excuse my ignorance, but where is a 22 or 21 on 0x2014030B, or a 23 or 22 on 0x20140514 ?
22 binary is 10110, 21 binary is 10101, 23 binary is 10111, none of those patterns are in any of those two numbers... what am i missing?

You are missing MR8
EDIT: tRCDW/A and tRP_WRA are lower for other reason. Try yours on Cryptonight and then mine - u'll see the diff.
Hint: ARB_DRAM_TIMING.ACTRD/ACTWR can go lower

[MikeBuzz]

Are there any publicly available custom memory strap timings for the rx 400 series? (samsung, elpida, or hynix)

Here's the Samsung strap I'm currently working on:
777000000000000022CC1C0010625C49D0571016B50BD50900400700140514207A8900A00300000 0191131399D2C3617

It's the 1750 strap with RRD=5, FAW&32AW=0.  It's stable at 2100 on my Sapphire Rx470.  The previous custom strap I tried was based on the 1625 strap, and I would start getting a lot of errors over 2000.  I just started working on it today, so there's more tweaking to do (like trying a lower tRC for RAS).

Nicely done
Lets see the final results.

Small adjustments to your timing based on my experience : 777000000000000022CC1C00CE615C45C0571016B30CD50900400700140514207A8900A00300000 0151031399D2C3617

Using that strap i am getting 29.5mhs @ 1180/2050

[sp_]

What is the most you can squeeze out of a r9 390 ?

[KL0nLutiy]

Are there any publicly available custom memory strap timings for the rx 400 series? (samsung, elpida, or hynix)

Here's the Samsung strap I'm currently working on:
777000000000000022CC1C0010625C49D0571016B50BD50900400700140514207A8900A00300000 0191131399D2C3617

It's the 1750 strap with RRD=5, FAW&32AW=0.  It's stable at 2100 on my Sapphire Rx470.  The previous custom strap I tried was based on the 1625 strap, and I would start getting a lot of errors over 2000.  I just started working on it today, so there's more tweaking to do (like trying a lower tRC for RAS).

Nicely done
Lets see the final results.

Small adjustments to your timing based on my experience : 777000000000000022CC1C00CE615C45C0571016B30CD50900400700140514207A8900A00300000 0151031399D2C3617

is it suit for sapphire rx 480 (Samsung)? 

[laik2]

What is the most you can squeeze out of a r9 390 ?

A LOT
watercooled 390 can hash ~37/8

[Eliovp]

What is the most you can squeeze out of a r9 390 ?

A LOT
watercooled 390 can hash ~37/8

Definitely! You can crank those babies up (390 Nitro's) to as good as 40Mh. (Huge OC though..)

[nerdralph]

Original Samsung 4G ( your particular GPU ) 1625
555000000000000022CC1C00CE596B44D0570F1531CB2409004AE700 [ 0B03 | 1420 ] 7A8900A003000000170F2E36922A3217

--> MC_SEQ_MISC1
 -- MR0
    WL = 3,  CL = 22,  TM = 0,  WR = 23,  BA0 = 0,  BA1 = 0,  BA2 = 0,  BA3 = 0
 -- MR1
    DS = 0,  DT = 1,  ADR = 1,  CAL = 0,  PLL = 0,  RDBI = 0,  WDBI = 0,  ABI = 0,
    RES = 0,  BA0 = 0,  BA1 = 1,  BA2 = 0,  BA3 = 0

Original Samsung 4G 1750
777000000000000022CC1C0010626C49D0571016B50BD509004AE700 [ 1405 | 1420 ] 7A8900A003000000191131399D2C3617

--> MC_SEQ_MISC1
 -- MR0
    WL = 4,  CL = 23,  TM = 0,  WR = 25,  BA0 = 0,  BA1 = 0,  BA2 = 0,  BA3 = 0
 -- MR1
    DS = 0,  DT = 1,  ADR = 1,  CAL = 0,  PLL = 0,  RDBI = 0,  WDBI = 0,  ABI = 0,
    RES = 0,  BA0 = 0,  BA1 = 1,  BA2 = 0,  BA3 = 0

I think you are off by +1 with the MR0 CAS latency.  SEQ_CAS_TIMING has CL=21(0x15) for the 1625 strap, and CL=22(0x16) for the 1750 strap.

Excuse my ignorance, but where is a 22 or 21 on 0x2014030B, or a 23 or 22 on 0x20140514 ?
22 binary is 10110, 21 binary is 10101, 23 binary is 10111, none of those patterns are in any of those two numbers... what am i missing?

The CAS latency in MR0 is just four bits (A3-A6), so it is based on a table lookup.  H5GQ1H24AFR supported all possible latencies from 5 to 20.  Micron's EDW4032BABG brief says "Programmable CAS latency: 6–27", so some latencies in the range cannot be programmed.  I don't have a Samsung datasheet for the K4G4 series (or any Samsung for that matter), so I would have to reverse-engineer the values from the straps by comparing the MR0 values to CL from SEQ_CAS_TIMING.

[Truthchanter]

Are there any publicly available custom memory strap timings for the rx 400 series? (samsung, elpida, or hynix)

Here's the Samsung strap I'm currently working on:
777000000000000022CC1C0010625C49D0571016B50BD50900400700140514207A8900A00300000 0191131399D2C3617

It's the 1750 strap with RRD=5, FAW&32AW=0.  It's stable at 2100 on my Sapphire Rx470.  The previous custom strap I tried was based on the 1625 strap, and I would start getting a lot of errors over 2000.  I just started working on it today, so there's more tweaking to do (like trying a lower tRC for RAS).

Nicely done
Lets see the final results.

Small adjustments to your timing based on my experience : 777000000000000022CC1C00CE615C45C0571016B30CD50900400700140514207A8900A00300000 0151031399D2C3617

Thanks! Nice improvement over the regular 1750 strap. Now the question is... will this 1750 samsung strap work with 480s with samsung (and then both 4gb and 8gb?)

[Eliovp]

Are there any publicly available custom memory strap timings for the rx 400 series? (samsung, elpida, or hynix)

Here's the Samsung strap I'm currently working on:
777000000000000022CC1C0010625C49D0571016B50BD50900400700140514207A8900A00300000 0191131399D2C3617

It's the 1750 strap with RRD=5, FAW&32AW=0.  It's stable at 2100 on my Sapphire Rx470.  The previous custom strap I tried was based on the 1625 strap, and I would start getting a lot of errors over 2000.  I just started working on it today, so there's more tweaking to do (like trying a lower tRC for RAS).

Nicely done
Lets see the final results.

Small adjustments to your timing based on my experience : 777000000000000022CC1C00CE615C45C0571016B30CD50900400700140514207A8900A00300000 0151031399D2C3617

Thanks! Nice improvement over the regular 1750 strap. Now the question is... will this 1750 samsung strap work with 480s with samsung (and then both 4gb and 8gb?)

If you have one of the first 4G samsung batches, it will work and even improve even more. (because you can unlock those to 8G)
If you have a newer batch of those 4G samsung's, it will most probably run but won't run stable.

Greetings

[Truthchanter]

Are there any publicly available custom memory strap timings for the rx 400 series? (samsung, elpida, or hynix)

Here's the Samsung strap I'm currently working on:
777000000000000022CC1C0010625C49D0571016B50BD50900400700140514207A8900A00300000 0191131399D2C3617

It's the 1750 strap with RRD=5, FAW&32AW=0.  It's stable at 2100 on my Sapphire Rx470.  The previous custom strap I tried was based on the 1625 strap, and I would start getting a lot of errors over 2000.  I just started working on it today, so there's more tweaking to do (like trying a lower tRC for RAS).

Nicely done
Lets see the final results.

Small adjustments to your timing based on my experience : 777000000000000022CC1C00CE615C45C0571016B30CD50900400700140514207A8900A00300000 0151031399D2C3617

Thanks! Nice improvement over the regular 1750 strap. Now the question is... will this 1750 samsung strap work with 480s with samsung (and then both 4gb and 8gb?)

If you have one of the first 4G samsung batches, it will work and even improve even more. (because you can unlock those to 8G)
If you have a newer batch of those 4G samsung's, it will most probably run but won't run stable.

Greetings

Interesting thanks! I have the old ones and actually used one of your old public bios on em

[laik2]

Are there any publicly available custom memory strap timings for the rx 400 series? (samsung, elpida, or hynix)

Here's the Samsung strap I'm currently working on:
777000000000000022CC1C0010625C49D0571016B50BD50900400700140514207A8900A00300000 0191131399D2C3617

It's the 1750 strap with RRD=5, FAW&32AW=0.  It's stable at 2100 on my Sapphire Rx470.  The previous custom strap I tried was based on the 1625 strap, and I would start getting a lot of errors over 2000.  I just started working on it today, so there's more tweaking to do (like trying a lower tRC for RAS).

Nicely done
Lets see the final results.

Small adjustments to your timing based on my experience : 777000000000000022CC1C00CE615C45C0571016B30CD50900400700140514207A8900A00300000 0151031399D2C3617

Thanks! Nice improvement over the regular 1750 strap. Now the question is... will this 1750 samsung strap work with 480s with samsung (and then both 4gb and 8gb?)

If you have one of the first 4G samsung batches, it will work and even improve even more. (because you can unlock those to 8G)
If you have a newer batch of those 4G samsung's, it will most probably run but won't run stable.

Greetings

Interesting thanks! I have the old ones and actually used one of your old public bios on em

The idea of custom timings is to replace only certain straps, not the whole vbios. I always use oem vbios with which the GPU arrives( if the vendor didn't push new one but that's very rare ).
As Wolf confirmed in a PM, hynix doesn't have defined bit for higher CLmrs above 20. It's not actually reverse engeneering, mostly u decode the highest strap and assume that CLmrs and tCL are at their highest bit.

[nerdralph]

Hint: ARB_DRAM_TIMING.ACTRD/ACTWR can go lower

I think I've figured out ACTRD.  It's the delay between successive READ commands to the same row(page).  It doesn't seem to be mentioned anywhere in the Hynix datasheet, nor in any of the GDDR product briefs I've looked at.  I had incorrectly assumed that back-to-back reads from the same row were possible.  With ETH mining (on AMD cards) each DAG access results in 2x 32-byte reads from 2 GDDR chips (128 bytes total).
The delay between ACTIVATE and READ is RCDR, and in the default Samsung straps use ACTRD = RCDR + 1.  Knowing the way DRAM works, ACTRD should be much lower than RCDR, but by how much?  A paper by nVIDIA suggests ~50%. https://www.cs.utah.edu/~dkopta/papers/DRAM-SIGGRAPH14_post.pdf

I tried reducing ACTRD to 16, and while it seems stable so far, the speed improvement is tiny (less than 0.5%).  So is this Samsung strap as good as it gets for Eth mining?
777000000000000022CC1C00CE615C45C0571016B30CD50900400700140514207A8900A00300000 010103139962C3617

[laik2]

Hint: ARB_DRAM_TIMING.ACTRD/ACTWR can go lower

I think I've figured out ACTRD.  It's the delay between successive READ commands to the same row(page).  It doesn't seem to be mentioned anywhere in the Hynix datasheet, nor in any of the GDDR product briefs I've looked at.  I had incorrectly assumed that back-to-back reads from the same row were possible.  With ETH mining (on AMD cards) each DAG access results in 2x 32-byte reads from 2 GDDR chips (128 bytes total).
The delay between ACTIVATE and READ is RCDR, and in the default Samsung straps use ACTRD = RCDR + 1.  Knowing the way DRAM works, ACTRD should be much lower than RCDR, but by how much?  A paper by nVIDIA suggests ~50%. https://www.cs.utah.edu/~dkopta/papers/DRAM-SIGGRAPH14_post.pdf

I tried reducing ACTRD to 16, and while it seems stable so far, the speed improvement is tiny (less than 0.5%).  So is this Samsung strap as good as it gets for Eth mining?
777000000000000022CC1C00CE615C45C0571016B30CD50900400700140514207A8900A00300000 010103139962C3617

In this version lowering ACTRD for eth won't give you much(it may go worse though...just keep an eye in the gap between actrd/actwr).
There are a few more things that can gain you additional hash but won't be much. The best I did for my MSI Armor 4G 470 was 30.2 at 1148/2075 but was unstable due to high mem temp(no heatsinks on the modules...). You might try lowering tRCDR, but based on my exp...it will throw more errors, also tRC a few bits "might" improve 0.1% which is irrelevant(why risk stability to gain such a small improvement). Try setting WR(Write recovery) 1 bit after CLmrs...or don't...Testing, testing, testing.

[phobosq]

I'm trying to make some experiments as well, but so far all failed. Every time I get to desktop after flashing a BIOS with custom straps, I get "Thread stuck in device driver" BSOD in 10-30 secs from OS load. I have Sapphire Nitro RX 480 4 GB with Samsungs, OS is Windows 10 x64. I tried 1625 strap with TRRD 5, 1750 strap with TRRD 5 and 1750 with TFAW/T32AW = 0, all with the same result. I suspect that injecting custom straps into BIOS using Polaris BIOS Editor might be the cause here. Anyone experienced similar problems?