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Author Topic: [RELEASE] Avalon Reference  (Read 17397 times)
dan99
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May 16, 2013, 03:19:56 AM
 #61

How is the BOM and comms protocol coming along for release?

We really need the BOM and communication protocol and power supply current estimates...
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May 16, 2013, 07:41:46 AM
 #62

Some people have asked about the FPGA bitstream. It makes sense that the FPGA bitstream would be one of the last things they provide in order to work out any bugs. It could be changed very last minute.

On the other hand, it should be noted that they want to keep the bit stream to themselves. Do we know that they don’t mind completing with others using their reference board design? They might have just released the design as a form of documentation with no plan of allowing other to use it as a competitive product. Technically this is very easy. The Spartan 6 allows its bitstream to be encrypted - this makes it impossible to steal the bitstream.

Oh, and BTW, I know others are designing board which require no FPGA, but until we have communication protocol specifications we don’t know if that approach will work, or is even possible.

I don’t mean cry the sky is falling, but do we actually have a commitment on their intention with the ref board release? Personally, I’m planning on using the klondike design, but wanted to be clear that there are still risks.

Drew
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May 16, 2013, 09:50:09 AM
 #63

Some people have asked about the FPGA bitstream. It makes sense that the FPGA bitstream would be one of the last things they provide in order to work out any bugs. It could be changed very last minute.

On the other hand, it should be noted that they want to keep the bit stream to themselves. Do we know that they don’t mind completing with others using their reference board design? They might have just released the design as a form of documentation with no plan of allowing other to use it as a competitive product. Technically this is very easy. The Spartan 6 allows its bitstream to be encrypted - this makes it impossible to steal the bitstream.

Oh, and BTW, I know others are designing board which require no FPGA, but until we have communication protocol specifications we don’t know if that approach will work, or is even possible.

I don’t mean cry the sky is falling, but do we actually have a commitment on their intention with the ref board release? Personally, I’m planning on using the klondike design, but wanted to be clear that there are still risks.

Drew

You are right.
However, they are selling bare chips. So they have some incentive to support the DIY scene too.
Yes, it's two conflicting positions, from an economic view.
It is not conflicting if they have "the greater good of bitcoin" in mind.
And from all I have seen from Avalon, I am very sure exactly that is the point.

Oh, and kudos for not wasting your time playing in the bitcointalk sandbox, Yifu. I really mean it, I much prefer you to do real work instead!

Ente
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May 16, 2013, 10:41:07 AM
 #64

Looks like BitSyncom pushed a new commit that has a datasheet with some comm protocol descriptions.

EDIT: For the lazy, the new document: https://github.com/BitSyncom/avalon-ref/blob/master/SPEC/A3256Q48-130507-V03-EN.pdf

Also: https://github.com/BitSyncom/avalon-ref/blob/master/UNLICENSE

Lookin' good, team Avalon!

goodney
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May 16, 2013, 07:13:14 PM
 #65

Thanks for the update BitSyncom!

One critical piece seems to be missing from the chip datasheet. How do you set the difficulty for the shares? Or is it fixed?

Also, is the HDL code for the FPGA coming?

-a[g
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May 16, 2013, 07:59:58 PM
 #66

Thanks for the update BitSyncom!

One critical piece seems to be missing from the chip datasheet. How do you set the difficulty for the shares? Or is it fixed?

Also, is the HDL code for the FPGA coming?

-a[g


is their a way to set the fan speed at 100%?
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May 16, 2013, 08:10:31 PM
 #67

This looks pretty impressive.  Wish I  knew what the hell I am looking at.  Shocked Huh

Aim - Slide.0
1J6UeiXtBYXmpA6uajRs3aJpUD1Tsj1CF3 - Tips?
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May 16, 2013, 08:38:35 PM
 #68

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How do you set the difficulty for the shares? Or is it fixed?
You don't; all core mining algorithms designed to-date work to solve difficulty 1, as do these ASICs.  The controlling software is responsible for filtering out shares that don't meet the required difficulty.

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May 16, 2013, 08:44:55 PM
 #69

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How do you set the difficulty for the shares? Or is it fixed?
You don't; all core mining algorithms designed to-date work to solve difficulty 1, as do these ASICs.  The controlling software is responsible for filtering out shares that don't meet the required difficulty.

I dont have any experience but wouldnt that mean there is hashpower going lost when it calculates things that cant be used and thrown away?

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May 16, 2013, 08:56:16 PM
 #70

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I dont have any experience but wouldnt that mean there is hashpower going lost when it calculates things that cant be used and thrown away?
Nope; and besides, all mining algorithms work this way.

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May 16, 2013, 09:02:42 PM
 #71

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I dont have any experience but wouldnt that mean there is hashpower going lost when it calculates things that cant be used and thrown away?
Nope; and besides, all mining algorithms work this way.

Now i remember... the difficulty was no var in hashing... it was only the border at which height a block could be found. When it was below no block was found.

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May 16, 2013, 09:41:39 PM
 #72

Also, is the HDL code for the FPGA coming?

Looking at point 10 it seems like the HDL code will be open source: http://store.avalon-asics.com/?page_id=9605
goodney
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May 16, 2013, 11:05:21 PM
 #73

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How do you set the difficulty for the shares? Or is it fixed?
You don't; all core mining algorithms designed to-date work to solve difficulty 1, as do these ASICs.  The controlling software is responsible for filtering out shares that don't meet the required difficulty.

Thanks... help me out here to clarify my thinking:

At difficulty 1 the target will be: 0x00000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

Which is 32 leading zeros. This divides the 256-bit hash space in 2^32 segments. This means on average one out of every 2^32 hashes will be a valid share. So one Avalon chip at 256Mh/s will return a valid share once every 16 seconds.

-a[g
fpgaminer
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May 17, 2013, 01:59:47 AM
 #74

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At difficulty 1 the target will be: 0x00000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

Which is 32 leading zeros. This divides the 256-bit hash space in 2^32 segments. This means on average one out of every 2^32 hashes will be a valid share. So one Avalon chip at 256Mh/s will return a valid share once every 16 seconds.
Yup, you've got it right.

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May 17, 2013, 02:13:20 AM
 #75

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At difficulty 1 the target will be: 0x00000000FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF

Which is 32 leading zeros. This divides the 256-bit hash space in 2^32 segments. This means on average one out of every 2^32 hashes will be a valid share. So one Avalon chip at 256Mh/s will return a valid share once every 16 seconds.
Yup, you've got it right.
Yes, except the Avalon is designed to do partial nonce ranges. So in practice you give each one a start nonce value and let it run some period suitable for the none to reach the value of the next range, after which it's wasting cycles. The controller needs to know when a range should be done and send more work. This divides the total nonce time by the number of Avalon in a chain.

rassalas
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May 24, 2013, 11:40:42 PM
 #76

/topic as promised.

https://github.com/BitSyncom/avalon-ref

will be updated continuously within a next few days.

I have a burning question,  I've sifted through the Github docs, but am having a hard time figuring out what cad software was used to create the pcbdoc and the Schdoc files. 
I'm assuming the BOM files were also generated by the same Cad program.  Anyone know?
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May 25, 2013, 12:15:06 AM
 #77

/topic as promised.

https://github.com/BitSyncom/avalon-ref

will be updated continuously within a next few days.

I have a burning question,  I've sifted through the Github docs, but am having a hard time figuring out what cad software was used to create the pcbdoc and the Schdoc files. 
I'm assuming the BOM files were also generated by the same Cad program.  Anyone know?
Rassalas
Altium Designer. They do have a free viewer for Windows on their web site. No Linux sadly.

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May 25, 2013, 01:40:28 PM
 #78

/topic as promised.

https://github.com/BitSyncom/avalon-ref

will be updated continuously within a next few days.

I have a burning question,  I've sifted through the Github docs, but am having a hard time figuring out what cad software was used to create the pcbdoc and the Schdoc files. 
I'm assuming the BOM files were also generated by the same Cad program.  Anyone know?
Rassalas
Altium Designer. They do have a free viewer for Windows on their web site. No Linux sadly.

And the viewer is not free... gotta register.
ecliptic
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May 26, 2013, 03:38:14 AM
 #79

iirc they made PDFs of the schematics, but i think they forgot and made it only of say, page #2 of a 2 page document, on some of them

the gerbers should be able to be viewable at least
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May 26, 2013, 01:59:41 PM
 #80

Awesome release! Thanks!

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