DIY FPGA Mining rig for any algorithm with fast ROI

[dragonmike]

It all looks very good on paper... The only thing is that if the coin prices keep falling, even fpga's won't be able to save us... Bleh!

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[GPUHoarder]

Whoosh

Are you going to share or just boast?

Read the rest of senseless’ comment - no one actually has 100kh cryptonight on one chip. He was making a commentary on how whole coins are making fork decisions based on comments in this post.

Actually from the claims, the Dwarf boards could do 100kh/s at $4000 price-point. If true, ie.

I’d be really interested to see those claims be accurate. I feel like my cryptonight7 is pretty optimal and those numbers are just insane.

Have you assessed their latest videos?

There’s nothing that can’t be faked in a video.

[ciciteng]

Wohooo... my batch of NEXYS Atrix-7 board is ready for this.
Do you still stay in the original plan to release the bitstream around end of this month, right?
Keep up the good work dev! ;-)

[The Endless Chain]

Can workstation cards become useful for mining ? Damn ! They're gonna teach us FPGA next year in college.

You mean the FirePro type GPUs? Definitely. I have many many older FirePro cards that had plenty of memory bandwidth but underpowered (or over powered depending how you look at it) cores compared to the current gen. This cards got large page table support and some other niceties because of who the customers were. The also support an FPGA on the PCIe bus directly writing into / readying from their GPU memory (albeit at PCIe speeds). This works great with something like ETH, because you can do all the compute heavy Keccak off GPU but still use all the memory bandwidth.

Totally get this & as a propeitor of a very large box of FirePro's given to me 2 weeks ago. My question is this, you mentioned 24 mh/s per GPU, is this in conjunction w/the FPGA?

[cryptaioracle]

After spending a lot of time in this thread, I met someone that "knows" a fair amount about this topic (arguably, more than anyone else in the entire world...). 

According to them, Intel is not planning on flooding anything.  Intel has practically liquidated their sales team and only Alterra customer is actually Intel itself.  In fact, they are having a lot of problems in the 10nm process and not able to make it work.

Recent releases of their FPGA lines have had numerous technical issues. So if anything, Intel's line is all but dead.  Leaving Xilinx as the lion share of the market won't give them much reason to lower prices. What I heard is that if anything, they are raising costs...

So, we need to all keep working on this. But from my intel (pun intended), a lot of the comments about pricing seem overly optimistic...

I'm pretty sure intel's plan is to flood the market. Why else would they be developing hybrid cpu/fpgas (like APUs) or why would they bother to create the CCIX interconnect? They're definitely going to flood the market.

Not exactly flooding the market with cheap ultrascale+ class products ...

https://www.anandtech.com/show/12773/intel-shows-xeon-scalable-gold-6138p-with-integrated-fpga-shipping-to-vendors

sampling now to special customers. spendy and only an arria 10.

it'll be quite a while before we're seeing affordable integrated stratix10 / x86 products that mom and pop can afford.

I think our definitions of flood the market differ. You're thinking about it from a consumer level -- It will eventually be that way -- But not in the next 12 months. If intel had the same practices as Xilinx, the Xeon 4116 system I just built would have cost me $100,000... Not $6,000... And I would have had to design my own motherboard, because they wouldn't have allowed me to produce their reference design... I don't think it's unreasonable to expect a $500-1000 unit cost on a large Stratix or Ultrascale+ part with HBM2 once production is moving 100K units a month. If Xilinx has their way, that part would cost $5,000-10,000 at "volume". If Intel increases their market share by expanding the market, and making these chips available at the enterprise level for hardware acceleration of databases, web servers, etc.... It's not unreasonable to think they could move 100K units a month at a $500-$1000 cost.. Amazon is currently leasing Xilinx fpgas. Do you think AWS would be interested in including FPGA logic in every single one of their servers? What about tencent? What about Baidu? What about every other provider on the planet? There's a storm on the horizon and it's going to be beautiful to watch.

The value of these devices in the server markets is in the 100s of billions. Far beyond their value in crypto markets, defense, etc, IMO. Xilinx has been very short sighted in their attempt to make profit. The world needs low cost FPGA. Not having it is preventing major advancements in computing.

[cryptaioracle]

these fpga threads are killin' me, can someone just make a plug-and-play fpga miner and sell it to me already?

Couldn't agree more...

We are working on it stealthily.

[senseless]

these fpga threads are killin' me, can someone just make a plug-and-play fpga miner and sell it to me already?

Couldn't agree more...

We are working on it stealthily.

Who's "we"? You mean "Bitmain"?

Edit: Apologies, I went back and saw your original post on May 8.

After spending a lot of time in this thread, I met someone that "knows" a fair amount about this topic (arguably, more than anyone else in the entire world...).  

According to them, Intel is not planning on flooding anything.  Intel has practically liquidated their sales team and only Alterra customer is actually Intel itself.  In fact, they are having a lot of problems in the 10nm process and not able to make it work.

Recent releases of their FPGA lines have had numerous technical issues. So if anything, Intel's line is all but dead.  Leaving Xilinx as the lion share of the market won't give them much reason to lower prices. What I heard is that if anything, they are raising costs...

So, we need to all keep working on this. But from my intel (pun intended), a lot of the comments about pricing seem overly optimistic...

Yes, their 10nm FPGA are terrible... I'm starting to wonder if it's a vaporware product...  

All jokes aside, I don't think your friend and us are talking about the same thing. If the situation at Intel is as bad as he believes, comparatively, the situation at Xilinx has to be a lot worse.

[cryptaioracle]

these fpga threads are killin' me, can someone just make a plug-and-play fpga miner and sell it to me already?

Couldn't agree more...

We are working on it stealthily.

Who's "we"? You mean "Bitmain"?

Edit: Apologies, I went back and saw your original post on May 8.

After spending a lot of time in this thread, I met someone that "knows" a fair amount about this topic (arguably, more than anyone else in the entire world...).  

According to them, Intel is not planning on flooding anything.  Intel has practically liquidated their sales team and only Alterra customer is actually Intel itself.  In fact, they are having a lot of problems in the 10nm process and not able to make it work.

Recent releases of their FPGA lines have had numerous technical issues. So if anything, Intel's line is all but dead.  Leaving Xilinx as the lion share of the market won't give them much reason to lower prices. What I heard is that if anything, they are raising costs...

So, we need to all keep working on this. But from my intel (pun intended), a lot of the comments about pricing seem overly optimistic...

Yes, their 10nm FPGA are terrible... I'm starting to wonder if it's a vaporware product...  

All jokes aside, I don't think your friend and us are talking about the same thing. If the situation at Intel is as bad as he believes, comparatively, the situation at Xilinx has to be a lot worse.

That was the second part of the conversation... didn't quite get there yet. I'm hoping for more information to share with the group next week. But the general feed back was "not positive" in terms of the future for these products. Google has their own ASIC's for HPDC, Bitmain seem to be getting into that business too. There are rumors of 7nm coming out next year (potentially)? That doesn't leave a lot left to be said...

On the other hand there is always crypto mining Who knows if that even makes sense, but at least there are a bunch of people working on it. If I had a goal out of this it wouldn't be to save the FPGA industry.  It would be to distribute as much hashing power (and quidproquo energy density thereof) as quickly as possible in a totally and completely decentralized way. Timer... start!

[skablast]

I haven't understood if I can use  my 5 xilinx xcs20 with one of those bitstream for something miner related or I will have to sell them

[Belg]

I haven't understood if I can use  my 5 xilinx xcs20 with one of those bitstream for something miner related or I will have to sell them

If I have found the documentation for the correct XCS20 ( https://www.xilinx.com/support/documentation/data_sheets/ds060.pdf ) then I very much doubt that you would be able to use them for mining since they have only 950 logic cells.
They were also end-of-lifed several years ago.

[vrdelta]

Anyone got a miner that can use the VCU1525 to test? I don't need bitstreams.

[GPUHoarder]

Anyone got a miner that can use the VCU1525 to test? I don't need bitstreams.

You’ll have to be more specific on algorithms, and the comm interface in your bitstreams.

[patata]

Anyone know what the plan and time frame for x16r support are?

[ilia_2s]

Anyone know what the plan and time frame for x16r support are?

Hi. The X16 is a chain of 16 algos. There is no one FPGA-chip have enough resources (logic cels) to place a X16.

[melpheos]

Anyone know what the plan and time frame for x16r support are?

Hi. The X16 is a chain of 16 algos. There is no one FPGA-chip have enough resources (logic cels) to place a X16.

You need two chained but the dev must have some serious FPGA Kungfu skill

[ilia_2s]

Anyone know what the plan and time frame for x16r support are?

Hi. The X16 is a chain of 16 algos. There is no one FPGA-chip have enough resources (logic cels) to place a X16.

You need two chained but the dev must have some serious FPGA Kungfu skill

There is no any special "KungFu" for it. Maximum hashrate will be limited to FPGAs interconnection (transceivers bandwidth, FiFo buffers etc.). Therefore, Final Interconnection bandwidth have a 10-100x less speed than actual hashrate in one chip.

[Longsnowsm]

Is there a step by step posted somewhere on how to build one of these?  What kind of results are you seeing with a DIY rig? 

[Coinkarlonline]

Hi,

Really interesting thread! I am beginning to mine using FGPA boards. I have been GPU and asic mining for the past year or so and have been interested in the FGPA side of things since hearing of it recently. I have purchased a Terasic DE0-Nano-SoC Development and Education Board to begin my learning. Can you say if any of your algo's will be compatible with the board mentioned? 1GB DDR3 ram and ARM dual processor.

Best,

Karl.

The DE0-Nano-SoC is a great board to get into learning this stuff. I have this and a few of the Max10 50kLE boards that I occasionally use for initial RTL hardware evaluation because their just so easy to work with. Vivado and Xilinx’s tools are steeper learning curve, but definitely doable.

With that said, the Cyclone V 5CSEMA4U23C6N on that board is about 1/5th the logic of what I’m proposing and while it has high-speed DMA to the ARM cores, it doesn’t have any high speed IO such as PCIe to other peripherals. That makes it tough to use outside of single small algorithms (I.e. Keccak).  The $199 version of the M.2 has ~100 Logic Elements and the $329 version has more than 200, capable of running at higher speed. The top package also has 1GB DDR3. Peak power consumption is around 15W from on-board M.2


Here’s an update summary for those catching up on this thread:

1. A few of us have been working on algorithms on FPGAs, and they’re profitable. Whitefire990 intents to release his with miner/dev fee and others of us have decided to share with the community in various forms as well.

2. On the high end the VCU1525, based on the VU9P is a very good candidate for this. It is currently a Xilinx development board on promotion for $3995, but only very small batches are being produced and the price is set to go up. Some algorithms require connecting multiple with high speed links to achieve the best performance.

3. Senseless (and possibly self, if I can be helpful) have been organizing essentially a group buy - but with FPGAs it’s less of a group buy and more of a group build. That is expected to ramp up the VCU1525 style (some power/cooling improvements)  availblility in a similar price envelope to Xilinx dev version. Working on production in US and Europe so it can be available everywhere.

4. I’ve also decided to reveal one of the smaller FPGA options in the $200-350 price envelope that I had developed for internal use and deploy, to provide an entry level option. It has a slightly different set of capabilities from the big VCU1525, but for many things it does scale.

For both hardware offerings from the community (and possibly others) orders are expected to start in June.

These boards are not so much for Ethash (though they can be used to assist/accelerate GPUs in it) , or Equihash. They excel , can improve total system performance on, or are at an advantage on Keccak (and most SHA3 candidate) , Phi variants, NIST5, Timetravel10, Lyra/LyraRev2, etc.

Someone else can chime in if I missed anything.

Hi GPU Hoarder,

Thank you for the detailed response! Apologies for my delayed response I have been trying to wrap my head around Verilog and VHDL since receiving the board. The Keccak algo you mentioned is this available online? Or direct through Whitefire? Interesting project above also, I will be following progress.

Best,

Karl.

[ilia_2s]

Is there a step by step posted somewhere on how to build one of these?  What kind of results are you seeing with a DIY rig? 

No, There is no sources was released by OP or anybody else for building and testing on real board.

[whitefire990]

Anyone know what the plan and time frame for x16r support are?

Hi. The X16 is a chain of 16 algos. There is no one FPGA-chip have enough resources (logic cels) to place a X16.

You need two chained but the dev must have some serious FPGA Kungfu skill

There is no any special "KungFu" for it. Maximum hashrate will be limited to FPGAs interconnection (transceivers bandwidth, FiFo buffers etc.). Therefore, Final Interconnection bandwidth have a 10-100x less speed than actual hashrate in one chip.

Sorry this is not correct.  The bandwidth between the two FPGA's is 320GBps which supports the 512 bit intermediate result x 625MHz, so the hash rate of two FPGA's connected does not suffer from the interconnect.