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Author Topic: DIY FPGA Mining rig for any algorithm with fast ROI  (Read 98589 times)
whitefire990
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May 30, 2018, 04:53:45 PM
 #961

Anyone know what the plan and time frame for x16r support are?

Hi. The X16 is a chain of 16 algos. There is no one FPGA-chip have enough resources (logic cels) to place a X16.
You need two chained but the dev must have some serious FPGA Kungfu skill

There is no any special "KungFu" for it. Maximum hashrate will be limited to FPGAs interconnection (transceivers bandwidth, FiFo buffers etc.). Therefore, Final Interconnection bandwidth have a 10-100x less speed than actual hashrate in one chip.

Sorry this is not correct.  The bandwidth between the two FPGA's is 320GBps which supports the 512 bit intermediate result x 625MHz, so the hash rate of two FPGA's connected does not suffer from the interconnect.
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whitefire990
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May 30, 2018, 04:54:46 PM
 #962

So, today is 5/30, the target launch day.  The website and initial downloads will be up by tomorrow night (5/31 late in the evening).  I will post again once it is live.

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May 30, 2018, 05:00:37 PM
 #963

thanks whitefire waiting anxiously for more details Smiley
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May 30, 2018, 05:01:59 PM
 #964

So, today is 5/30, the target launch day.  The website and initial downloads will be up by tomorrow night (5/31 late in the evening).  I will post again once it is live.



Hyped... Sad that Europe is left aside until august but who knows maybe it can start earlier Smiley
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May 30, 2018, 05:21:41 PM
 #965

So, today is 5/30, the target launch day.  The website and initial downloads will be up by tomorrow night (5/31 late in the evening).  I will post again once it is live.



Is there any way to actually get the cards at this point? Jason from Avnet never got back to me.
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May 30, 2018, 06:47:52 PM
 #966

The bandwidth between the two FPGA's is 320GBps which supports the 512 bit intermediate result x 625MHz, so the hash rate of two FPGA's connected does not suffer from the interconnect.

Its true for theoretical bandwidth in datasheet. Yes, but not in real implementation. Even if you have a 320GBps between FPGA you can reach only 320 000 / 512 = 625 MHash/sec. But in real project it will have additional speed lost in input/output part.
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May 30, 2018, 06:56:56 PM
Last edit: May 30, 2018, 07:21:01 PM by senseless
 #967

So, today is 5/30, the target launch day.  The website and initial downloads will be up by tomorrow night (5/31 late in the evening).  I will post again once it is live.



Is there any way to actually get the cards at this point? Jason from Avnet never got back to me.

We're working on it. It's slow going but i'm cautiously optimistic about what the next couple of weeks worth of meetings would hold for myself and others in this thread.  

Also, my project is unrelated to whitefire's other than we've been doing the same things independently. We're not the only 2, there are a few in this thread that have all been doing the same thing in secret for quite awhile now. His performance is much better than mine (and some of the others) for these logic based algos. I haven't seen him mention any numbers for memory algos, but I believe my numbers may end up higher than his there. This is why I'm in favor of a community shell and community bitstreams. There may be others in the community who can achieve performance even better than myself and whitefire! Let's see what the community engineers can do Smiley

The bandwidth between the two FPGA's is 320GBps which supports the 512 bit intermediate result x 625MHz, so the hash rate of two FPGA's connected does not suffer from the interconnect.

Its true for theoretical bandwidth in datasheet. Yes, but not in real implementation. Even if you have a 320GBps between FPGA you can reach only 320 000 / 512 = 625 MHash/sec. But in real project it will have additional speed lost in input/output part.

Not necessarily. #1) Really short < 1m distance. #2) We're not required to follow any sort of network level protocol. One of the engineers I'm working with was operating 10Gbps over distance using 2 pins from the FPGA.

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May 30, 2018, 08:45:19 PM
 #968

So, today is 5/30, the target launch day.  The website and initial downloads will be up by tomorrow night (5/31 late in the evening).  I will post again once it is live.



Is there any way to actually get the cards at this point? Jason from Avnet never got back to me.

I just got this from Jason today:

"We discussed pricing and I was able to get Xilinx to agree to a tiered pricing model.  Initial orders up to 5 units get the promotional price of $3995.00USD each.  Any orders beyond that will be priced at $4995.00USD (special price for Zetheron customers)."

Try calling him directly.  He is a great guy, who is very knowledgeable and willing to answer any questions you have.
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May 30, 2018, 09:00:36 PM
 #969

Also, my project is unrelated to whitefire's other than we've been doing the same things independently. We're not the only 2, there are a few in this thread that have all been doing the same thing in secret for quite awhile now. His performance is much better than mine (and some of the others) for these logic based algos. I haven't seen him mention any numbers for memory algos, but I believe my numbers may end up higher than his there. This is why I'm in favor of a community shell and community bitstreams. There may be others in the community who can achieve performance even better than myself and whitefire! Let's see what the community engineers can do Smiley
I admire you for this.
I think there are a lot of us here without the skills to do what you are but who would happily pay for that service.
Currently the fpga market is very difficult to break into. I'm not only talking about Joe Retail who's got 3 grand to spend on hardware, but also "mid-size" budget guys or even limited companies with a few dozen grand or up to 100-200K for whom this could mean a major investment opportunity. The only lead we have are people like Whitefire, yourself or Dwarfminer... "Faceless" nicknames on an internet forum (no offense meant - just being literal). The latter could literally be a 50/50 chance of being a total scam.

I don't know any fpga programmer. The only distant connection I had flat out turned away any offer under a 100 grand for any type of project like this.

Me and my friends would happily dish out good money if we knew the project had legs and a basis to stand on.

I'm hoping this will go forward! Smiley



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May 30, 2018, 09:42:19 PM
 #970

So, today is 5/30, the target launch day.  The website and initial downloads will be up by tomorrow night (5/31 late in the evening).  I will post again once it is live.



Is there any way to actually get the cards at this point? Jason from Avnet never got back to me.

I just got this from Jason today:

"We discussed pricing and I was able to get Xilinx to agree to a tiered pricing model.  Initial orders up to 5 units get the promotional price of $3995.00USD each.  Any orders beyond that will be priced at $4995.00USD (special price for Zetheron customers)."

Try calling him directly.  He is a great guy, who is very knowledgeable and willing to answer any questions you have.

Same here, never responded.

Bitrated user: dhinendra.
sephir69
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May 30, 2018, 11:55:10 PM
 #971

So, today is 5/30, the target launch day.  The website and initial downloads will be up by tomorrow night (5/31 late in the evening).  I will post again once it is live.



Is there any way to actually get the cards at this point? Jason from Avnet never got back to me.

I just got this from Jason today:

"We discussed pricing and I was able to get Xilinx to agree to a tiered pricing model.  Initial orders up to 5 units get the promotional price of $3995.00USD each.  Any orders beyond that will be priced at $4995.00USD (special price for Zetheron customers)."

Try calling him directly.  He is a great guy, who is very knowledgeable and willing to answer any questions you have.

Same here, never responded.
Both guys in the first msg responded to me within a few days.  Crypto one on for bittware isn't ready and Jason put my order order for the 1525 through no problem except a few forms you have to fill out and cc info.  I did use a corporate email so maybe that was the trick.
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May 31, 2018, 12:52:15 AM
 #972

"We discussed pricing and I was able to get Xilinx to agree to a tiered pricing model.  Initial orders up to 5 units get the promotional price of $3995.00USD each.  Any orders beyond that will be priced at $4995.00USD (special price for Zetheron customers)."

Special pricing huh ?

~ LOL ~
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May 31, 2018, 03:23:09 AM
 #973

"We discussed pricing and I was able to get Xilinx to agree to a tiered pricing model.  Initial orders up to 5 units get the promotional price of $3995.00USD each.  Any orders beyond that will be priced at $4995.00USD (special price for Zetheron customers)."

Special pricing huh ?

~ LOL ~

Wow - yes this is NOT special pricing.

Give us a few days, early next week at the latest.
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May 31, 2018, 08:42:40 AM
 #974

So, today is 5/30, the target launch day.  The website and initial downloads will be up by tomorrow night (5/31 late in the evening).  I will post again once it is live.



Will you provide a basic manual / help for your miner? thanks

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May 31, 2018, 08:52:11 AM
 #975

"We discussed pricing and I was able to get Xilinx to agree to a tiered pricing model.  Initial orders up to 5 units get the promotional price of $3995.00USD each.  Any orders beyond that will be priced at $4995.00USD (special price for Zetheron customers)."

Special pricing huh ?

~ LOL ~

Wow - yes this is NOT special pricing.

Give us a few days, early next week at the latest.

Glad Jason with avnet.com ignored my email. Good things comes to those who wait.
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May 31, 2018, 09:19:00 AM
 #976

Its really hard to get a good feeling about this FPGA thread, if it is real and how difficult it will be to set up.
I have found someone selling it in my country, only to companies though so thats something i would have to create lol.

But best to wait and see. Also it is hard to know if the coin developers will be able to actualy make it FPGA resistant as LUX says they will do.
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May 31, 2018, 01:42:56 PM
 #977

What is the best FPGA board that will support your software relation price-performance
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May 31, 2018, 03:57:09 PM
 #978

But best to wait and see. Also it is hard to know if the coin developers will be able to actualy make it FPGA resistant as LUX says they will do.

Unless coin developers work with FPGA devs to develop an algo or series of algos, they will have an exceptionally hard time developing a coin that couldn't be put on an FPGA in a very short time.  Coins can be FPGA resistant, but FPGA bitstreams can be developed far faster than ASICs.  In the end it's only a matter of time between when a coin forks, and an FPGA can adapt.
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May 31, 2018, 04:04:48 PM
Merited by Longsnowsm (1)
 #979

But best to wait and see. Also it is hard to know if the coin developers will be able to actualy make it FPGA resistant as LUX says they will do.

Unless coin developers work with FPGA devs to develop an algo or series of algos, they will have an exceptionally hard time developing a coin that couldn't be put on an FPGA in a very short time.  Coins can be FPGA resistant, but FPGA bitstreams can be developed far faster than ASICs.  In the end it's only a matter of time between when a coin forks, and an FPGA can adapt.

Those coin devs should be more concerned about someone creating a secret 90nm asic for $500,000 and 51% attacking their coin.

If the algo change is not very big it will take less than a day to modify for a fork. For instance, zcoin, they forked away by changing their lyra2 parameters. We would only need to change 4 lines of code to adapt. The longest part of making the change would be waiting for the bitstream to compile. But, they increased the memory usage beyond what is available on the chip - so we won't be able to mine them again until we get our HBM2 memory. But, we will, and we will once again achieve perf above and beyond GPUs. Then what are they going to do? There's no change they could make at that point where we couldn't correct for it in the same day they made the change.

So, now that I know zcoin will try to pow change if they find out I'm mining on it, why would I ever be public about it? Maybe I should go spend $500,000 secretively and be 99% of their hashrate? (I wouldn't do this. But, Bitmain and others would.)

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May 31, 2018, 04:50:45 PM
 #980

Up to this point secret ASIC's or FPGA's have had the objective of being secret... So they are below the radar and below the threshold of easy detection.  But what if that changed?  It really is a very powerful weapon if you wanted to attack.   There is a bigger picture here that seems to be overlooked by the coin communities. 
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