Avalon4 with global shipping can be purchased here!

[Rabinovitch]

I am waiting for Avalon4, that will be ~1TH/s (1~1.2) at ~700W for only ~490USD. I would like to buy such a device right now. Not in 2 monthes. Now.

[1714979661]

1714979661

[1714979661]

1714979661

[ChuckBuck]

I am waiting for Avalon4, that will be ~1TH/s (1~1.2) at ~700W for only ~490USD. I would like to buy such a device right now. Not in 2 monthes. Now.

That's always the conundrum with buying Bitcoin miners, isn't it?

Buy lesser efficient hardware now, or more efficient hardware in a month or 2, but not after a few difficulty jumps.  Risky either way.

[Finksy]

I am waiting for Avalon4, that will be ~1TH/s (1~1.2) at ~700W for only ~490USD. I would like to buy such a device right now. Not in 2 monthes. Now.

That's always the conundrum with buying Bitcoin miners, isn't it?

Buy lesser efficient hardware now, or more efficient hardware in a month or 2, but not after a few difficulty jumps.  Risky either way.

But it's not a conundrum really, you can buy 28nm finished products right now for BTC1.28/ TH/s that draw ~800W at the wall (S3's).  They don't have 2 months, they need it out now. If I was them I would be giving chips away to developers to get their products and testing done ASAP.  The only way they will make money on this is if people fall for the pre-order trap, like they always do.

[sikke]

https://en.bitcoin.it/wiki/Avalon4

Wiki is updating

[marto74]

Can you provide contact for technical questions?
If you look in the datasheet PDF of the chip:

page 6 :
 (2) All input/output data is 32bit aligned, and send out in MSB (that means
lowest bit send first).

page  8 :
 All data is sent in MSB, means high bit, high byte and high word is sent first

Wich one is correct ?

[marto74]

Next questions:

1.  Can we do like that  :Power  0.9 V -> pin1 VDDIO  [ chip N]  pin42 VDDIO -> pin1 VDDIO [chip N+1], without connection on PCB between pin1 and pin 42 on the same  ASIC

2. VDDPLL is pin 14 ; pin 29 is  NC(not connected). Can we use  pin 29 for VDDPLL to the next ASIC

3. The NC (not connected ) pins do they have some function ( i.e. Inputs, Outputs etc.)

[Avalon-pr]

These are interesting...

Anyone want to go in together on a batch of the samples?

-a[g

sold out!   
restock needs few days

[Avalon-pr]

thank you very much for your time and attention.

please see this:

page 6 :
 (2) All input/output data is 32bit aligned, and send out in MSB (that means
the highest bit send first).

page  8 :
 All data is sent in MSB, means high bit, high byte and high word is sent first

Can you provide contact for technical questions?
If you look in the datasheet PDF of the chip:

page 6 :
 (2) All input/output data is 32bit aligned, and send out in MSB (that means
lowest bit send first).

page  8 :
 All data is sent in MSB, means high bit, high byte and high word is sent first

Wich one is correct ?

[marto74]

Thank you .
As far I still do not have contact for technical questions .
Please andswer to the rest questions .
Here is a new one too:
Not clear how to calculate the register contents for the clock Configuration
Fout = Fref * NF / NR * Next -> what means Next?
Now is calculated OD, BWADJ.
Why there are 3 Clock Configuration words in the A3222Q56 Configure Sequence - (Clock Configuration 2, Clock Configuration 1, Clock Configuration 0)

[xiangfu]

Hi

You can email to this mailing list:
  http://lists.canaan-creative.com/cgi-bin/mailman/listinfo/discussion
(All canaan creative developers was there)

And you can join the IRC #avalon @freenode.net
(Most of the developers was there)

I can answer one of this question. [Why there are 3 Clock Configuration words]:
Because there ~4000 cores inside the Avalon4 28nm. so we split those 4000 cores to three group. then we can make the three group work at different clock. this is a great design I think. that can make all core work at best condition base on voltage and clock.

I will update your questions to wiki(en.bitcoin.it/wiki/avalon4) then others can see the answers.

BTW:
I have forward your question to mailing list. (http://lists.canaan-creative.com/pipermail/discussion/2014-September/thread.html)
Xiangfu

Thank you .
As far I still do not have contact for technical questions .
Please andswer to the rest questions .
Here is a new one too:
Not clear how to calculate the register contents for the clock Configuration
Fout = Fref * NF / NR * Next -> what means Next?
Now is calculated OD, BWADJ.
Why there are 3 Clock Configuration words in the A3222Q56 Configure Sequence - (Clock Configuration 2, Clock Configuration 1, Clock Configuration 0)

[xiangfu]

Forward to mailing list.

Xiangfu

Next questions:

1.  Can we do like that  :Power  0.9 V -> pin1 VDDIO  [ chip N]  pin42 VDDIO -> pin1 VDDIO [chip N+1], without connection on PCB between pin1 and pin 42 on the same  ASIC

2. VDDPLL is pin 14 ; pin 29 is  NC(not connected). Can we use  pin 29 for VDDPLL to the next ASIC

3. The NC (not connected ) pins do they have some function ( i.e. Inputs, Outputs etc.)

[marto74]

Avalon 4 samples are here , just waiting for the testboard  next week to start test

[technobitMarto]

http://s17.postimg.org/4wsjsy0r3/first_board.png

Technobit
Avalon 4   16 chip board
Hex16a4

[technobitVesi]

Avalon 4 board ready for tests

http://s14.postimg.org/w0e92f38h/20141008_190749.jpg

http://s14.postimg.org/4oj012yht/20141008_190802.jpg


upload pictures online

Regadrs: Vesi

[dogie]

I'm guessing no top side heatsinks then?

[technobitVesi]

I'm guessing no top side heatsinks then?

We prepared both bottom and top to be ready.
Will see
http://s27.postimg.org/5h7j89pc3/20141008_204531.jpg

[ManeBjorn]

Will the heatsinks have a better orientation for cooling in say a hot/cold isle data center setup?

I'm guessing no top side heatsinks then?

We prepared both bottom and top to be ready.
Will see

[dogie]

This company's rating has been updated in the Manufacturer Trustworthiness thread.

[This message won't be monitored, discuss your concerns in the thread.]

[technobitVesi]

Avalon 4 single chip running @ 24 Ghs - 16W


http://s8.postimg.org/fsqosp6wl/24_GHs_1_chip_23_GHs_real_for_several_hours.png

[Rabinovitch]

Ok, waiting now for cheap, highly efficient, quiet and cold miner.