I post and respond to this PM here, since it is of general relevance.


There are two levels of experience I can share. The first one is from the logical link layer / SW side (my domain): when I got the FPGA simulator to work on the cgminer driver I attached it to RPi's SPI interface, sent it a job and got a result returned. I was like 'whoa if that is how the real chip works, that will be easy'. Then when I got to test the driver on a real A1, the same driver still worked and the chip crunched the whole nonce range in 160ms. I was like 'whoa, this is incredibly easy!'. If you take a look at the initial cgminer driver, you'll see what I mean.

Then there is the productizing level - which is not my domain and I can only report from my experience with HW hacking sessions over lots of sleepless nights. There it turns soon out that the 'easy' preconditions the chip requires (as depicted here) are not exactly trivial to ensure. You might end up opening your Champagne bottle after seeing your board hashing for hours flawlessly - just to notice it stopped over night. And after endless debug sessions to find out that one chip reset itself since your power supply had a larger than tolerated ripple at a very specific temperature. Or that one single bit in inter-chip SPI communication toggled due to parasitic effects from adjacent PCB layers - which as result kills a chip chain in case a command is interpreted wrongly by the chip.


So in essence: yes, the chip is really that easy. Ensure you keep the requirements met and it will hash right away. As for communication, there is not much you can mess up there: I have been trying the RPi's SPI port, bit-banging over GPIO, or proxying the access over STM32 SPI port - all work with master SPI clocks between 5 kHz and 10 MHz.

To make a working product out of it is a different story then. Getting it to hash for some hours is still easily doable - but building a board that runs for months untouched under various environmental conditions is not. That is why Bitmine has not yet started shipping products. And that might be the reason we see only marto74 reporting back successful operation of his design - he has a great experience with his Avalon / BitFury boards and started off from a design with verified signal integrity. Others starting from scratch might need to learn first.

In retrospect my advice would be: follow a KISS approach; start with a single or 2-chip design first and ensure your DCDC is capable to keep up the required power stability (for reference: marto74 and Bitmine provide 50A); in a second step, copy paste that design to form larger chains. While the A1 is meant to be chained up to 250 chips, 8-chip chains seem to be a sweet spot between overhead and communication latency.


Good Luck.

Yes, why? RSP-3000-12. Or do you refer to the rated 2400W for 12V?

No need to speculate about that. What we use when testing locally in the Bitmine labs is a meanwell 3kW PSU - the wall of PSUs in the picture posted is exactly that.

There are some left until end of this week. Please follow order process described in OP.

Update: Sample Chips available from Bitmine

Folks, please do not be stupid / childish here - be more constructive instead. Samples have been sent out to 20+ parties, would be more interesting to hear of some progress (besides marto's) instead of carrying some fight from other threads into this one.


Sample Chips Availability in Bitmine's Online-Shop
As announced earlier, with the confirmations that chips are working, the time frame for free samples got closed. Sample chips will remain available in low quantities through Bitmine's online-shop here.


DIY Chip Distribution closing
Along with samples, I supplied a dozen projects with 50+ chips for their first test runs. This weekend I will ship the remaining chips to get converted to mining rig. With that, this DIY chip distribution will end. I expect that those who validate their design will anyway order in larger quantities, smaller miners can easily stick together and do a group buy from Bitmine.

I will post the closing date more formal when I know my assembly options, this is just to inform you of the approaching closure.

So far it seems I have been the only one using it - if and when the user base broadens, the correct way is to a) clean the code up, b) rebase it on current cgminer head, and c) get it accepted upstream. Since this needs some initial and ongoing maintenance effort, I need to know if anyone is using the driver as-is for own designs.

And that is one point: all designs currently being worked on are based on existing drivers already integrated in cgminer. Take marto74's for example: the uC on the 8-chip board will encapsulate the control of the A1 chips and to cgminer that board will look like any other HEX based one, fully accessible with the existing driver. Same goes for WASP, burnin, intron. My driver is meant to attach to a system's SPI port directly and most probably will serve only as template for full featured drivers or initial testing.



There are no related restrictions documented or known and I am not aware that anyone from the working designs is keeping some defined bring-up order. The only requirement documented is the reset sequence (1s low, then 1s high before first command is sent).

Where do you draw the line here? Aren't hobbyists part of the DIY scene, or what would be your classification of a hobbyist?

I believe making chips available in lots of 50 is exactly aiming at hobbyists. Or are you saying there are people out there investing time to develop some mining boards and then produce only one of them? I won't expect that, i.e. if someone has a working board, he should have a vital interest to order at least 50 chips.

Please let me know if I am not aware of common use-cases out there and I will consider.

Update: Chips arrived and re-shipped


Chip Distribution
Bitmine received the first lot of chips on Thursday. Orders that have been paid by then where shipped on Friday, the remaining ones will do after I receive the payment in full.

With that, also the 2nd wave of samples have been sent / will be sent on Monday to
Good Luck with your designs.


New Terms for free Sample Chips
In the past few days I received around 30 requests for samples. While glad to hear about so many DIYers, given the fact that most of them were from folks just registered to the forum, I need to assume the service is misinterpreted as free chips giveaway.

Generally, with the availability of the A1 in volumes, the distribution of free sample chips ended. For serious developers I will still left a supply option open, but to distinguish them from free-riders I have to adapt the terms as follows: 2 sample chips are shipped to developers at their effective costs of $250. That amount will be deducted from the payment of that developer's first order of 50+ chips - with that they effectively become free samples again.

I'm sure you agree that this change is required to be able to provide best support to the serious developers.

Well, this OTOH I can comment on, since I am testing the chips.

Several things to take into account here:
1) Those preliminary power estimates were given based on GF's numbers on their processes and simulations. Those following the chip developments over the past 2 years know how those estimates can be quite in line (KnC) or 400% off (...). Whether the final chip will provide those figures remains speculation until you actually test the chip and measure the numbers.

2) The samples we have now under test are inferior re packaging compared to the final ones. This affects thermal properties as well as voltage supply restrictions. As a matter of fact, we were limited in the measurements we could perform so far and need to wait for the final chips for the remaining ones.

3) The numbers we were able to turn from expectations into facts are very good. At nominal clocks (800MHz) we pull like 1.1J/GH from wall. Deducting PSU and DCDC losses and considering sample chip inefficiency, we are at 0.6-0.7 J/GH at chip. While with the above limitation we can not yet test the other modes (turbo / low-power), we nevertheless pushed the chip to 1GHz clock and measured the expected 32GHps.


Generally my impression is that the chip is well in the announced specs, but given how sensitive folks are to facts, I understand why Bitmine waits for the final chip to present binding numbers.

Great, almost there. The two badly performing chips out of 8 is a little bit higher failure rate than what I observed with the samples (~10%), the real chips won't suffer from that (assuming they are tested).

Thanks for confirming that longer chip-chains work.


Cheers

This is outside of what I am able to respond, since most depends on who your partners are, i.e. PCB manufacturer, component sourcing, assembly, testing, etc. This info obviously is company confidential.

In my day-job I work as SW-engineer to bring up prototypes, and from there I know that - if time does matter and price does not - 10 days from working prototype to mass production is a good rule-of-thumb.

FWIW: as already posted in this thread before, I have the very first chip order in queue that I am using to supply DIY folks, and I was informed just today that the first wave of chips got out of China right before New Year and is on its way to Europe (see related post).

With that and before the speculation and conspiracy takes over again: assume for a moment that chips were not yet delivered. It is as easy as that.

I bought my chips for delivery in November and obviously don't like the delay either, but I fail to see how it helps our case splattering the thread with the always same questions and speculations.


Obviously I am biased by the additional information I get through my consulting work with Bitmine, but if it helps your confidence I assure you that there are no bad intentions with this one. The people are working their butts off to get this thing started, and with the chips finally on their way stay tuned for an official announcement these days.

Update: Chips shipped to Europe

Status
I was informed that the first wave of chips made it to HK before Chinese New Year and is on its way to Switzerland.

Delivery is expected by end of this week, DIY projects should have them in hand next week.


Remaining Sample Chips
I have the following names on my list for remaining sample chips:

If you requested samples but are missing on that list, please contact me again. Same goes of you are on the list but don't need the samples any more.


Chip Orders / Availability
All projects that placed orders will be contacted today with payment details. You are given time to finalize the payment until end of this week.

End of this week is also the guaranteed availability for the chips, since unsold ones are converted to mining rig ASAP.



Cheers,
zefir

Hm, no - both tested designs (Bitmine, marto74) use multi-chip-chains. Not sure what the WASP folks are going for, but no test results so far from their side.

Worst case you need to ensure that chip is not broken. If you have the second sample available you could double check.


Above that, please PM me for a more interactive support.

Please double check:

• keep RESETn low for a second, then at RESETn=1 wait for another second before you send the first command
• connect SDI_L to SDO_L to close the SPI chain
• 0x0100 (BIST_START) is a one-shot command: enumeration works only once after HW-reset, subsequent calls return 0 for chip count

From here I would guess SDI_L and SDO_L are not connected, leaving the SPI chain open. With that, all broadcast commands fail - among others the chip can not finalize its chip enumeration, thus responds only to 0xa00 - which btw. is an illegal command, since READ_REG is addressed to individual chips and not defined for broadcast.


Let me know if you need further help.

Update: Chip Distribution re-opened

Now that the first independent developer confirmed A1 chips are working as specified and word is that chips are sent out from China before the Chinese New Year, chances to get the first wave of chips in January look good.

Therefore I am re-opening the chip distribution effective immediately. The below details are added to the OP, please always refer to the wording in the OP, in case I gradually extend it with further information.


Cheers,
zefir

---

Chip Distribution in DIY Volumes (50+)

About
Bitmine is offering Coincraft A1 chips in 500+ volumes to the masses, which for DIY folks might be unpractical. Therefore I am distributing some of the chips I ordered for personal use to the scene with non-profit intentions. Take this as a symbolic compensation for 2013's disaster the DIY scene was hit by. I am herein offering up to 5000 chips from the first chips in volumes in lots of 50 chips. The price is what Bitmine asks for the chips at time of order, with an 8% surcharge to cover S&H expenses.

Is this for me?
There was a great confusion with the initial announcement, so to clarify here: this offer is NOT for you if

• you need more than 500 chips
  => order at Bitmine and you will save the 8% surcharge and even get discounts on higher volumes
• you want a manufacturer to build your board(s)
  => order your boards at the manufacturer of your choice, he will get better prices with higher volumes
• you want to organize a group buy
  => please organize your group buy so that you can make a 500+ order at Bitmine directly; I do this at no cost to support the open source DIY scene and don't want to run into multi-party deals and related troubles

How to order
I expect only a limited number of orders and will therefore follow a manual order processing.

• orders are placed via email to this address (please leave the Gmail alias suffix intact)
• with the order, please include your shipping address (if possible with phone number for express); if you are concerned about your privacy, please use PGP encryption (my public key is in my sig)
• chips are offered at Bitmine's price for 500+ chips at time of order +8% (today 3.5$/GHps, including surplus: $4'725 / 50 chips)
• you will be asked for payment once I know chips are on their way to Switzerland
• payments will be in BTC only and based on BitStamp exchange rate at time of payment
• should I fail to ship your chips within 2 weeks after your payment, you will be refunded the exact amount of BTC you paid
• orders are processed FCFS, no pre-order, no down-payment
• buyer is in charge for taxes and customs

Good Luck!

Congratulations Martin, great work!

With that, you even beat Bitmine - who have one chip already running at 35GH/s but need to rework the inter-chip communication.

The 200 MHz is a typo I guess, since you need to run the chips with 800 MHz to get to 25 GH/s per chip (with all cores running).

AFAIK, my order is the very first chip order, so yes, that should be the same.

But frankly speaking: after the recent experiences I made with the habits in global chip business (I don't refer to Bitmine who themselves are only customers), I won't bet on ETAs or expectations given. The chains are that long that you need only one person within that chain to miss his bus to work and your ETAs become moot. That's why I stopped asking for delivery dates - chips will be here when they will be here.

This is not meant to discourage your efforts, just saying that it is not advised to order PCB assembly slots based solely on the expected dates given.

RFC: Lower bound SPI transfer Volume Estimation for A1 Chip Chains

I have been asked from different parties what the maximum chain length of the A1 chips is, and while the specs limits the addressable number of chips to 254, I tried to approach the potential limit from the communication side.

To have the chip continuously hashing, for each nonce range the absolute minimum command sequence consists of

• 1x 07 to send the job; command length: 30 words
• 1x 08 to get the result; command length: 4 words
  Note: this is the average - some jobs have more than one result, others have zero
• 1x 0a to get the queue state; command length: 5 words
  Note: this is the absolute minimum, might need to cycle poll

To get a command pushed through the chain of M chips, we need to push

• 2M words for broadcast commands
• 2N-1 words for unicast commands to chip N

With that, the number of word to write per job to chip N in a M-chip chain is
  (30 + 2N - 1) + (4 + 2M) + (5 + 2N - 1)
= (29 + 2N) + (4 + 2M) + (4 + 2N)
= 37 + 4N + 2M

For all chips in chain of M chips:
W = sum(N = 1..M) {37 + 4N + 2M}
  = M * (37 + 2M) + 4 * (M * (M + 1) / 2)
  = 37M + 2M^2 + 2M^2 + 2M
  = 4M^2 + 39M
  = M * (4M + 39)

For the ease of calculations, we assume W = 4M * (M + 10)

The lower bound of required words W to transmit for continuous hashing a chain of M chips with that is
  1: 44
  2: 96
  4: 224
  8: 576
 10: 800
 16: 1664
 20: 2400
 32: 5376
 40: 8000
 64: 18944
 80: 28800
128: 70656

A chip running at 800MHz finishes a nonce range in 4/25 seconds or 160ms.

Assuming an SPI duty cycle of D = 20% (polling causes idle times) the minimum SPI host clock to serve a chain of M chips is

W * 16 * 1/D * 1000 / 160 = W * 500Hz

Minimum host SPI clock frequency to operate a chain of M chips:
 1: 0.02MHz
 4: 0.11MHz
 8: 0.29MHz
16: 0.83MHz
32: 2.69MHz
40: 4.00MHz
64: 9.47MHz

At 800MHz core clock, the A1 internal SPI clock is 12.5MHz. Since it is required to keep external SPI clock below internal, we shall assume 64 chips to be the upper bound chain length to try.


Please review and let me know if something is wrong.

Well, if that happens my chip order runs into the 60+ days delay window given by the CPP and I will have the choice to take the full refund instead. I don't want to speculate on that, since still my hopes are to get supplied soon.