AFAIK we are slightly behind compared to the projections in the spreadsheet. Our hands are kind of tied with respect to the Klondikes and the Avalon clones since both of those projects (totally ~6th/s) are dependent upon Avalon chips being shipped arriving in a timely (lol) manner. I don't want to give specific estimates (especially the dreaded "2 weeks"^TM), but everything that can be done/prepped by Ken beforehand is being done (see one of ActiveMining-PRs first updates).

Progress with respect to eASIC is a little more difficult to comment on due to the NDA. Last I heard (and I'm one of those guys that has read every page on both this and the speculation thread) Ken was converting the BTC into USD to pay the NRE costs. We did learn that eASIC is, in fact, capable of dealing with 28nm chips thanks to the press release about Seagate and eASIC so that's some good news there.

If I have made any errors in the above statements, please correct them. On a more positive note, share price is growing nicely thanks to all the BTCgarden ipo money finally being returned.

One point about this that I believe could be a future game changer:

The European Parliament debates on and brings in laws across the European Union (US-based readers may or may not know much about this). All EU countries must and do, almost without exception, abide by EU law. Now the EU are largely VERY progressive especially on 'ECO' matters - they had for example started the phase out the use of high energy-use incandescent light bulbs by 2009, whereas in the US a similar ban has still to come into effect and in California for example it wont do until 2018!

http://en.wikipedia.org/wiki/Phase-out_of_incandescent_light_bulbs

What this means is that the industrial use of electricity by BTC mining companies may be heavily taxed in the future in Europe while in the US it remains unregulated for far longer. The EU parliament has a history of introducing eco laws that are unpopular with business but are popular with the public. I think it would be very easy for btc mining operations to be priced out of the EU given enough bad publicity about 'wasting' massive amounts of electricity. Germany has decided to abandon all of it's nuclear power stations       http://en.wikipedia.org/wiki/Energy_transition_in_Germany     by 2022, they are planning to go completely renewable. Power is an incredibly hot topic as a result in Germany and Germans are generally very eco minded. So it's easy to see them putting pressure on the legislative body/European Commission to introduce a carbon tax on BTC mining across the EU.

This is going to sound sarcastic, but I don't mean it to be.

Are you of the mindset that the US gov't can and will do whatever they want, on a world-wide scale, regardless of any law/restriction that is in place?

We currently have a location bedded down which can handle that power-draw (expandable up to 2.5MW) and an on-site chiller which will supply us with 5.5degC water-supply (in)
The heated water generated from the ASICs will go directly (out) toward heating a newly-built, medium-sized (20+ floors) skyscraper. Exactly how much of that heat will be re-used is unknown at this stage, and will probably change over time, but it helps that our deployment will happen at the start of the European winter.

This is for the primary location - we have that pretty much wrapped up, but we are looking into other locations that may be better able to handle the heat output, and work better for cost reduction and longevity of the mine (price/kWh). Please understand that buying energy at volume gets much better deals than retail/household prices.

(...)
Anyway, Electricity cost of 450Kw/h vs profit will be irrelevant for a long while.

I need some tech support from Vbs or Ken before getting back in ACTM.  

My brain's EECS well is almost dry.  Quantum lithography?  Sure, common knowledge.

Iterative vs. rolled vs. unrolled cores?  Ummm, ELI30 ploz....      

Which is more faster?  Which is ACTM using?

Will our giant semi-premade cores have better heat dissipation from being more widely spaced?

Is this stuff Top Secret, because NDA?

I find it pretty funny that you think vbs is "watching our backs". Vbs is a long-time, outspoken promoter and investor in ActM. It Streets never became ActM's PR person, it likely would've been Vbs. Do you have any proof that Vbs even knows what he's talking about? Any proof that he owns Labcoin shares? Any proof that he's not just spouting FUD in order to drive potential investor away from Labcoin to ActM?

I just find it funny that you're willing to put so much trust in someone who actually has a good motive to spread FUD here.

I think VBS is threatened by Labcoin.  It would be best if he just stayed in his own thread and make comments about Labcoin there.  The same should go for all "Spokes people" for company's.

Disclaimer

I also own both

[11:43] <labcoin_dev> Alright,the 130nm IC is designed to work at about 200 Mhz for core, with a total consumption of 0.8W per core, hashing performances of about 200 mhash per core, total speed will depend  on the overall output grade

[11:53] <+labcoin_dev> Chip frequency : 300Mhz, Process : 130nm CMOS, Die size: 4160,0000um2,    VDD : 1.2-1.5 V adjustable

[11:57] <zefy> So you've arranged them to fit more on the same size?
[11:58] <+labcoin_dev> we adopt a "sea-of-hashers" approach
[11:58] <dexX7> from vbs: "For that to be possible, not only each Labcoin core would have to be ~42% smaller [65/130*(6.5^2)/(7.1^2)] than each BFL core but also the Labcoin chip would magically operate at a higher frequency (300MHz vs 250MHz) while keeping the same power draw..."
[11:58] <+labcoin_dev> i remind you guys that the bitfury chip has up to 750 cores
[11:59] <+labcoin_dev> they also use the same approach, we chose this design because one of our guys was close to bitfury developments 2 months ago

[12:13] <ThickAsThieves> 6. How is it possible to create chips with a such much better performance than the competitors?
[12:14] <+labcoin_dev> ThickAsThieves, rolled cores instead of unrolled, sea-of-hashers approach
[12:15] <+labcoin_dev> as in sea-of-gates
[12:15] <+labcoin_dev> you can google this term and find out more about what it means technically

Technical Details (Translated from various Bitfury Posts)

• The design is built on the 65nm UMC Process (http://www.umc.com/English/process/a.asp)
• Bitcoin Engines: 756 Rolled cores (65 Cycles per Hash)
• Expected operational frequency: 250Mhz-900Mhz
• Packaging: QFN48
• Conservative design, could be 40% smaller
• Risk interconnect and transistor variations +/- 20%
• Core implemented using full custom design process (some global place & route)
• Number of transistors per "core": 55,000
• Power estimate obtained from hspice simulation
• Design optimised for low power and minimum size rather than high clock rate

Each chip is capable of 2.8-10.4Gh/s using a 756 core design
Estimated Chip Power Consumption: 1.96-7.26W (0.7W per 1Gh/s)
Estimated Power Consumption at Wall: 1.4W per 1Gh/s (<200W per 120Gh/s Device)

I am sure that AM is mining with 130nm.

No, AM are using 130nm, Avalon are the ones using 110nm.

Update

A lot of great thing happened last week. We wiped over the obstacles (infrastructure and paperwork) on deploying and put a lot of our available hashrate online. We also did a significant improvement (power, design, appearance) on the USB stick from the sample batch to the production batch.

For the discussion in the last few days, what we... I could say, is only that our IC design team had achieved fantastic results, as everyone could see and compare, with the most limited funds (barely more than 100k$ raised last August) and most inferior mask-set of choice (130nm which belongs to the antiquity era), and I'm proud of it.

How can this version be so much smaller than the earlier 180nm design? I assume this is more or less the 180nm chip design shrunk to 130nm, and the numbers seem right except for the size. How in the world can you fit 16 cores in that small area? I can't make sense of it. The 180nm version would be 5mmx5mm so this one should be a square with 5mm*130/180=3.6mm, no? 16 of these would be 14x14. Can anybody help me figure this out?

ASICMINER's next generation chips will be out by November... do you honestly think any of these IPOs will produce functional products by then? We don't know the specs of the next AM chips... but there is every reason to assume they will be in line with the specs these other companies are promising, if not superior.

The primary difference is that ASICMINER has proven that they can deliver.

TBH Vbs, i dont really know or understand what those two companies are promising. The lack of easily digestible, and consistent information/communication is at best, questionable.

ASICMiner has hit their glass ceiling and are basically floundering to be fair, simply because they are on old tech.

KnC's 28nm ASIC is at a similar efficiency to BitFury's 55nm ASIC. There's more to it than simply the size of the process. These 28nm ASICs sacrifice performance and efficiency for faster design and manufacturing and lower NRE costs. You can't just claim one chip is better than another because it uses a smaller process.

Just in case you don't know,  ASICMiner is mining with these oldhat tech 130nm "ASIC" chips.

Just back on this "real asic" - "semi-prefab-asic" question - SHA256 is an incredibly simple algorithm so I very much doubt a cell-based ASIC would be all that much faster than a pre-fab jobbie. If the ASIC needed to be super complex (more like a scrypt ASIC) - I can see cell-based would offer reasonably uplift in performance, but with the simplicity of SHA256 chips, pre-fab won't be much worse off.

Liken it to calculating pi in machine code, or any other programming language. Both are going to be able to do a pretty damn quick job of it - arguably compiled code will run as quickly as machine code doing the same thing. I'm guessing the differences might be around the 10-20% although I am absolutely 100% speculating without any knowledge of chip production.

Do you have any insight into how this differs from the "better" cell-based ASIC that I keep seeing referenced?

Can somebody explain to me the suggestion that a "28nm ASIC" is basically just a 28nm FPGA... I read the eASIC press release to mean they've simplified the process of designing ASIC's to a level on par (in simplicity terms) to coding an FPGA? In other words "We've got software which basically designs the ASIC for us, based on an algorithm" rather than "our 28nm asic's are actually fpga's"

Maybe I'm missing the point here, but a 28nm ASIC is an ASIC... There's absolutely no way anyone could get 16GH on an FPGA chip, or even a semi-FPGA chip (whatever that is). If we compare the "real 65nm ASIC" produced by BFL, at 4.5GH, with the apparently "not real 28nm ASIC" running at 16GH, by your suggestion the concept that a 28nm chip can hash at 16GH is impossible.

I'll freely admit I'm not an engineer, but I am a logical person, I code, and I understand the concepts and differences between FPGA's and ASIC's. What's being suggested simply doesn't compute.

To add some more details: the first batch contains 312 wafers * 2000 chips/wafer * 400 MH/s/chip = 249 TH/s. And according to the first post this batch should arrive mid september and the other batch will be ordered immediately after they receive/test the first batch. If this is all correct, a total of roughly 850 TH/s should be covered by the IPO.