We might get a bitstream into the board this week based on a re-build of standard stuff but for higher performance one of our own is probably about 4 weeks away. That's also dependent on what else we have to do in the next few weeks on other projects. There may be third party solutions available before our optimised solution is available. So don't expect spectacular bitstream results from us this week. You are going to have to be a bit patient on this. Our target this week is ensuring that the in-built programmer is totally rock solid, getting the production line more optimised, actually shipping boards and trying to get a standard bitstream working to our satisfaction. That's all on top of a large number of UK people being on holiday this week.

Although we have not had a massive amount of time to work with standard bitstreams but we have had some progress and can get a test nonce to run now using our CGminer based test harness. We still have some coms issues to resolve and that is the main area of work this week at the bitstream level.

I've done part of this http://hackaday.com/2011/12/30/so-you-wanna-learn-fpgas/
Must make more time free to do more, but at the moment diablo 3 is so much fun

The language choice doesn't really matter. This project is so simple conceptually that the normal reasons for chosing the language are immaterial. This project stresses later stages of the design flow. Your experience with classical sequential programming languages is probably even counterproductive. What really helps is understanding the basics of logic design: combinatorial and sequential logic, flip-flops, etc. as well as any previous experience with declarative or parallel programming languages.

Most of the time you will spend researching various ways of transforming your program to convince the toolchain to accept your idea of how the design should be laid out. If you use Xilinx ISE as your toolchain then be aware of the following:

1) dense LX150 design will require more than 4GB of RAM during the later stages of the workflow, make sure that your machine has at least 8GB and the OS is 64-bit.
2) Xilinx changed the toolchain front-ends (both for Verilog & VHDL) with their "-6" FPGA families. When using tutorials prepared around older Xilinx FPGA families you may experience problems related to the corner-case differences in the HDL implementations.
3) even very small designs on a large chip take comparatively long time to compile. By the time the toolchain reads the floorplan and pinout of the LX150 chip the whole workflow on the LX9 chip will be done. Therefore for the beginners I recommend obtaining $98 Avnet Spartan-6 LX9 kit. If you start with a full LX150 design, especially unrolled one, you will experience annoyingly long workflow iteration times, in the order of hour or two.

FPGA design is like playing tetris, chess and contract bridge all on the same board that is rectangular, not square.

On languages both VHDL and Verilog have similarities and relationships to C. VHDL probably is now the closest although the more advanced System Verilog is in there too. VHDL tends to have a bigger base in Europe and in the FPGA community. Verilog is strong in the US and in ASIC teams. We work with both but strongly biased to VHDL which is 80-90% of what we do. Things like "types" and "overloading" are used in VHDL and a very familiar concept to a C programmer. C programmers tend to have most difficulty dealing with the parallelism. It's a bit different handling 10000 things happening on a clock edge to 1 thing happeing in most CPUs.

Yup. The one I had linked to was a much smaller Arria II with only 45k LE.

I've done part of this http://hackaday.com/2011/12/30/so-you-wanna-learn-fpgas/
Must make more time free to do more, but at the moment diablo 3 is so much fun

How many of these boards can we expect to run on a single molex from an ATX PSU ? I have seasonic 1250 golds, so I hope they can run several of these plus a few 5970's. Could we expect to run like 3 5970's on the PCI E connectors and then 4-5 of these on the molex connectors and then maybe 2 on the extra PCI-E ?

I would like to run rigs with 3 5970's and 6-8 Quad FPGA's for a while, per rig.

Hmmm, 7-8.5 GH/s per rig at maybe 1100-1200 watts would be sweet.

This might get me to 40 GH/s...

Currently EldenTyrell has a custom bitstream which can push these same chips to 250MHash/s approx.

And BitFury has a custom bitstream pushing (liquid cooled I believe) LX150s (same chips as Cairnsmore) to 300MHash/s or more.

But it should be pointed out that neither of those has been "independently verified" by a third party.

So yes the chips have the potential to reach much higher hash rates using a new bitstream (essentially firmware for an FPGA).

But right now, I think Enterpoints goal is to get "icarus-like hashing per chip" (so 190-200mhash) out of them to get them in customers hands, with an easy method of usb updating the boards so that once a new/improved bitstream is available, they can be updated easily.