Just what is a clock buffer anyway?

[Bogart]

Hi Everyone,

We've been very busy recently, unfortunately I couldn't catch up with the forums. There is a correction to be made: Chips are not and were not flawed. We decided to add certain clock buffers to improve noise-resistance and possibly increase frequency even further. The improve in noise resistance was our real goal (average frequency increase across a full wafer can be a bi-product). The decision was made to increase the near 100% chance of success even more. We'll keep you posted. If you had any questions, please let us know.


Regards,
Nasser

So just what is a clock buffer?  What does one do, where is BFL likely to be adding them to their product, how many will they be adding, and why that number and location?

From the name, I can imagine some of the things one might do.  I could just google it, but discussing it here sounds like more fun.

Discuss.

[Keninishna]

I don't know physically what they will use for a clock buffer but the idea is to improve the signal and reduce noise. Like intel uses 3d tri-gate resistor tech as well as the use of the element hafnium to help with the clock at smaller die sizes. I could be a bit off but this is my understanding.

[abeaulieu]

Buffers themselves usually are implemented to keep noise from feeding back into another system or to create a delay in the signal (hinted at by the name buffer). A clock buffer is implemented more specifically to control rise and fall time of clock edges (google "slew rate"). This allows for the clock to be fanned out with more stability and less jitter.

[goxed]

http://hyperphysics.phy-astr.gsu.edu/hbase/electronic/buffer.html#c2

[mightycount]

It's something you add when you don't have a chip.. Eh?

[pieppiep]

You can think of an electric circuit like a network of waterpipes.
When you need a high level of water on the other side of the pipe you let water in. You try to keep the level at a certain hight at the beginning, water will flow until the level at the end is the same.
The same happens with electricity, but much faster. You rise the voltage at one end, current starts flowing and the voltage rises at the other end.
The parts in a chip for the calculation are usually very close together, so you just need a little current and a short time to rise the voltage.
The clock signal however, is needed at many places so the current to rise the voltage in many endpoints needs to be a lot higher.
The clock signal is not like a single pipe that needs to be filled with water, but a complete network of many pipes.
If you cut the pipe network into smaller pieces, the smaller pieces are filled much faster. At the end of the smaller pieces you place a device that will open a watertap to fill the part after it.
The clock buffer is something like this, it reacts on the clock and outputs more current than it receives so that the circuit can have a big clock network.

[ab8989]

The most accurate non-technical synonym I could think of is repeater or amplifier. The clock needs to be routed from one input pin into thousands or millions gates inside the chip that need clock and to do that there is a thing called clock-tree inside the chip, where the single input clock is divided into these millions of consumers. You cannot just use one metal connector strip to do that since the millions of consumers would each get just a tiny fraction of the input voltage or current available and that is obviously not going to be enough. Therefore you are forced to insert buffers ( repeaters ) into this clock tree to regenerate the clock signal characteristics as they degrade when the signal is being split. There are multiple layers of these buffers feeding another buffers feeding another buffers in the tree.

[eldentyrell]

It's what you add when you don't have chips.

[bitmar]

It's what you add when you don't have chips.

 you can also increase speed (for example from 40GH to 60 GH.) or improve power consumption or give a false date of shipment or be unpleasant for customers or troll competition.  You can do a lot of things when you do not have chips  

[Keninishna]

It's what you add when you don't have chips.

 you can also increase speed (for example from 40GH to 60 GH.) or improve power consumption or give a false date of shipment or be unpleasant for customers or troll competition.  You can do a lot of things when you do not have chips  

I believe thats called a clock block.

[elux]

Hi Everyone,

We've been very busy recently, unfortunately I couldn't catch up with the forums. There is a correction to be made: Chips are not and were not flawed. We decided to add certain clock buffers to improve noise-resistance and possibly increase frequency even further. The improve in noise resistance was our real goal (average frequency increase across a full wafer can be a bi-product). The decision was made to increase the near 100% chance of success even more. We'll keep you posted. If you had any questions, please let us know.


Regards,
Nasser

This is a clock bluffer.

[bitmar]

It's what you add when you don't have chips.

 you can also increase speed (for example from 40GH to 60 GH.) or improve power consumption or give a false date of shipment or be unpleasant for customers or troll competition.  You can do a lot of things when you do not have chips  

I believe thats called a clock block.

next "clock block" soon. I bet on performance increase from 60 to 90Gh (why ? -> bASIC - 72GH)

BFL employee 1 - "Hey, look at this, Tom has 72GH !!!"
BFL employee 2 - "Damn, we need to add more clock block"
BFL employee 1 - "Piece of cake, we have enough clock blocks for the whole year"
BFL employee 2 - " So, time to start operation clock block !!!"
BFL employee 1 - "but what do people will say?"
BFL employee 2 - "Fuck this, we will give them 90GH, so they can will wait a few more months, if this is not enough we will give them 200GH or more"
BFL employee 1 - "and later we will say that the Chinese have failed"
BFL employee 2 - "ok, Check in the calendar Chinese holidays"

[Bogart]

OK, those explanations make good sense, and are more or less in line with what I expected.

I imagine that a clock buffer, at one end, receives the signal from a clock source and demodulates it (digitizes it, quantizes it, whatever).  Then, based on its now digital interpretation of the input signal, it creates one or more new signals (maybe it has multiple outputs), which may have different characteristics than the input signal, such as amplitude (voltage), wave shape, and probably a delay (offset) relative to the input signal.

I can see this being does at the board level, but does it make sense also at the chip die level?

[MrTeal]

OK, those explanations make good sense, and are more or less in line with what I expected.

I imagine that a clock buffer, at one end, receives the signal from a clock source and demodulates it (digitizes it, quantizes it, whatever).  Then, based on its now digital interpretation of the input signal, it creates one or more new signals (maybe it has multiple outputs), which may have different characteristics than the input signal, such as amplitude (voltage), wave shape, and probably a delay (offset) relative to the input signal.

I can see this being does at the board level, but does it make sense also at the chip die level?

In VLSI design there is the concept of fan-out, which is the the number of gates that a gate has to drive. The larger the load on a gate, the more capacitance slows the rise and fall of the signal edge. You can't just take a clock source and hook it up to a couple hundred points around the chip as the capacitance is such that a minimum sized transistor can't drive it. You can increase the drive capability of the circuit by cascading stages making each stage about 4x larger that the last (see FO4) and by buffering the signal. Just increasing the drive capability of your main clock source isn't always the best answer though, and local clock buffers are often used for different logic blocks. It's basically two inverters in series. They aren't a cure-all though. You still run into skew, where the signal from your clock source arrives later at one part of the chip than another, and jitter, where the period of the clock isn't regular. If they already have a working design "without flaws", they better be damned careful adding clock buffers. Depending on how synchronous the design is, it's not trivial to change a lot in your clocking system without introducing new problems.

[eldentyrell]

In VLSI design there is the concept of fan-out, which is the the number of gates that a gate has to drive. The larger the load on a gate, the more capacitance slows the rise and fall of the signal edge. You can't just take a clock source and hook it up to a couple hundred points around the chip as the capacitance is such that a minimum sized transistor can't drive it. You can increase the drive capability of the circuit by cascading stages making each stage about 4x larger that the last (see FO4) and by buffering the signal. Just increasing the drive capability of your main clock source isn't always the best answer though, and local clock buffers are often used for different logic blocks. It's basically two inverters in series. They aren't a cure-all though. You still run into skew, where the signal from your clock source arrives later at one part of the chip than another, and jitter, where the period of the clock isn't regular. If they already have a working design "without flaws", they better be damned careful adding clock buffers. Depending on how synchronous the design is, it's not trivial to change a lot in your clocking system without introducing new problems.

This (emphasis added).  You don't screw around with the clock tree unless you absolutely have to.

[Inaba]

In VLSI design there is the concept of fan-out, which is the the number of gates that a gate has to drive. The larger the load on a gate, the more capacitance slows the rise and fall of the signal edge. You can't just take a clock source and hook it up to a couple hundred points around the chip as the capacitance is such that a minimum sized transistor can't drive it. You can increase the drive capability of the circuit by cascading stages making each stage about 4x larger that the last (see FO4) and by buffering the signal. Just increasing the drive capability of your main clock source isn't always the best answer though, and local clock buffers are often used for different logic blocks. It's basically two inverters in series. They aren't a cure-all though. You still run into skew, where the signal from your clock source arrives later at one part of the chip than another, and jitter, where the period of the clock isn't regular. If they already have a working design "without flaws", they better be damned careful adding clock buffers. Depending on how synchronous the design is, it's not trivial to change a lot in your clocking system without introducing new problems.

This (emphasis added).  You don't screw around with the clock tree unless you absolutely have to.

You should take Elden's words with a grain of salt.  He's pretty smart, but has a history of just talking out his ass, as evidenced by the fact that he just makes stuff up as he goes along:

It's utterly pointless to compare a standard-cell design to a full-custom design using transistor count.  Even between full-custom designs it's normal to see a 4x variation in area based on the foresight of the architect and the skill of the layout designer.  By the way, BFL doesn't use the phrase "full custom" to mean the same thing it means in the industry.

By the way, BFL doesn't use the phrase "full custom" to mean the same thing it means in the industry.

We don't?  Please elaborate. (I'm serious, I'm not being snarky.  If we/I am using it incorrectly, then I would like to use the proper term.)

Standard-cell ASICs and synthesis-flow ASICs are not considered full-custom chips.

The phrase "fully custom" is a BFL-ism that sounds a lot like "truthiness"  In fact the third google hit for "fully custom asic" on the entire interweb is BFL which ought to be a hint that it is a contortion of the usual industry terminology...

Emphasis mine. (Google "Fully Custom ASIC".  14k results, most of them not BFL. The ones that are BFL?  Someone else wrote it. (https://bitcointalk.org/index.php?topic=83985.0))

[eldentyrell]

has a history of just talking out his ass, as evidenced by the fact that he just makes stuff up as he goes along:

If you can't deal with the facts, go ad hominem...

In fact the third google hit for "fully custom asic" on the entire interweb is BFL which ought to be a hint that it is a contortion of the usual industry terminology...

Emphasis mine. (Google "Fully Custom ASIC"

The thread about BFL is still the third hit, more than a month after I wrote that; see screenshot below taken 29-Nov-2012 at 4:46pm PDT.  The second hit is also BFL-related but was started by somebody else, which still supports my statement that "fully custom" is a BFL-ism.  The butterflylabs.com website has apparently dropped down to #5 since I wrote that.

I'm glad you've started using less ambiguous terminology since then.  However I fear that with the latest post by Nasser that progress might be being undone…  Seriously, it just doesn't add up on several different levels, which is why I'm poking fun at it.  If Nasser posts real, self-consistent, credible details on what went wrong with the first mask set and what the plan for the respin is, I'll gladly switch my avatar back.  But I can't blame you for not wanting to give out that much information.



I've never heard of these Kromek people before (they seem to be more of an imaging company than a chip design company) and the Boeing hit is a typo since it's the only occurrence of "fully custom" anywhere on boeing.com.

[Bogart]

It's utterly pointless to compare a standard-cell design to a full-custom design using transistor count.  Even between full-custom designs it's normal to see a 4x variation in area based on the foresight of the architect and the skill of the layout designer.  By the way, BFL doesn't use the phrase "full custom" to mean the same thing it means in the industry.

By the way, BFL doesn't use the phrase "full custom" to mean the same thing it means in the industry.

We don't?  Please elaborate. (I'm serious, I'm not being snarky.  If we/I am using it incorrectly, then I would like to use the proper term.)

Standard-cell ASICs and synthesis-flow ASICs are not considered full-custom chips.

The phrase "fully custom" is a BFL-ism that sounds a lot like "truthiness"  In fact the third google hit for "fully custom asic" on the entire interweb is BFL which ought to be a hint that it is a contortion of the usual industry terminology...

Emphasis mine. (Google "Fully Custom ASIC".  14k results, most of them not BFL. The ones that are BFL?  Someone else wrote it. (https://bitcointalk.org/index.php?topic=83985.0))

Eh?  Are you trying to tell us that "Fully Custom ASIC" is the correct term?

I think this calls for...

http://googlefight.com/index.php?lang=en_GB&word1=%22Full+Custom%22+ASIC&word2=%22Fully+Custom%22+ASIC

[Crypt_Current]

It's what you add when you don't have chips.

 you can also increase speed (for example from 40GH to 60 GH.) or improve power consumption or give a false date of shipment or be unpleasant for customers or troll competition.  You can do a lot of things when you do not have chips  

I believe thats called a clock block.

Best post in thread 

[Inaba]

The thread about BFL is still the third hit, more than a month after I wrote that; see screenshot below taken 29-Nov-2012 at 4:46pm PDT.  The second hit is also BFL-related but was started by somebody else, which still supports my statement that "fully custom" is a BFL-ism.  The butterflylabs.com website has apparently dropped down to #5 since I wrote that.

Elden, you really need to stop when you're ahead.  If you even bothered to look at the screenshot you posted, you'd have noticed that Blazr used the term "Fully custom" and, in the VERY NEXT POST you corrected him.  So somehow, that's BFL's fault.  Yes... makes perfect sense.  Now, could you please stop making stuff up and talking out your ass?

For reference, it's this thread you are referring to, since you're far too busy to click the links you are citing as evidence about how silly BFL is being: https://bitcointalk.org/index.php?topic=117368.0

I'm glad you've started using less ambiguous terminology since then.  However I fear that with the latest post by Nasser that progress might be being undone…  Seriously, it just doesn't add up on several different levels, which is why I'm poking fun at it.  If Nasser posts real, self-consistent, credible details on what went wrong with the first mask set and what the plan for the respin is, I'll gladly switch my avatar back.  But I can't blame you for not wanting to give out that much information.

So, since you obviously know what you're talking about (can you sense the sarcasm?), could you point out where BFL has used "fully custom?"  I would trust what Nasser has to say far more than I would trust anything you have to say, since you can't even decipher a message forum correctly.  

Incidentally, this was the first post with regards to BFL's products, as you'll see in the quoted section, it says "full custom" not "fully custom."  But go on, tell me again how we don't know what we're doing, even though you insist that we are not doing a "full custom" or a "fully custom" ASIC, and how we're doing "Standard-cell ASICs and synthesis-flow ASICs are not considered full-custom chips."  Pretty much everything you've posted about BFL's technology has been... wrong.

I don't care if you switch your avatar or not, we've already demonstrated you don't know what you're talking about, so what the hell!