Custom RAM Timings for GPU's with GDDR5 - DOWNLOAD LINKS - UPDATED

[laik2]

dont be rude, you were too generic : "If u get 29MH on 2000 it means your timings are too tight and won't be as stable"

I appologize, it was a moment of weakness. I read now that I haven't specified with this specific strap he posted.
Of course you can get 29+ with even lower than 2000 but not with these specific timings.

[1715651675]

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[1715651675]

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[laik2]

Some hynix tests at doktor83's clocks:



One of my experimental straps:



Both with set tRAS

[laik2]

How about going in the other direction (NSFW): https://ottrbutt.com/tmp/ethwolf-03212017.jpg ?

See GPU 4.

My friend...this is pure terror over the hardware
I've sent screen to ElioVP a while ago doing almost 33 at 1211/2225, but that 1300/2275 is insane!

[nerdralph]

How about going in the other direction (NSFW): https://ottrbutt.com/tmp/ethwolf-03212017.jpg ?

See GPU 4.

Is that running AMDGPU-Pro 16.60 on kernel 4.10?

[laik2]

How about going in the other direction (NSFW): https://ottrbutt.com/tmp/ethwolf-03212017.jpg ?

See GPU 4.

Is that running AMDGPU-Pro 16.60 on kernel 4.10?

You can't run amdgpu-pro 16.60 on 4.4+ it won't compile without patching.
You run 4.10/11 with OSS amdgpu driver + ocl package from amdgpu-pro 16.60.

clinfo-amdgpu-pro                               install
libdrm-amdgpu-pro-amdgpu1:amd64                 install
libdrm-amdgpu-pro-dev:amd64                     install
libdrm-amdgpu-pro-utils                         install
libdrm-amdgpu1:amd64                            install
libdrm2-amdgpu-pro:amd64                        install
libegl1-amdgpu-pro:amd64                        install
libgbm1-amdgpu-pro:amd64                        install
libgbm1-amdgpu-pro-base                         install
libgbm1-amdgpu-pro-dev:amd64                    install
libgl1-amdgpu-pro-appprofiles                   install
libopencl1-amdgpu-pro:amd64                     install
opencl-amdgpu-pro-icd:amd64                     install

Linux ucm64xd 4.11.0-rc2-nvamd #1 SMP Mon Mar 13 20:30:11 EET 2017 x86_64 x86_64 x86_64 GNU/Linux

[nerdralph]

Sometimes loosening the timings is better, and clocking higher - specifically on Eth.

I've seen you mention loosening the CAS timings.  I tried bumping up tCL by 1, but still get crashes on the K4G4 at 2100.  So is it just loosening tCL that usually does the trick, or something else too?

You have to loosen it on the DRAM, too - you're loosening the tCL on the ASIC, but not the DRAM, throwing them off.

Interesting.  So the memory controller (or driver) isn't smart enough to take tCL from SEQ_CAS_TIMING and use same value for MR0 Cas Latency?
edit: I don't even understand how this would work at all.  If the controller is expecting the data 22 cycles after the read, but MR0 is programmed for 21, then wouldn't that cause a 100% error rate?

Here's a quote from the datasheet:
During READ bursts, the first valid data‐out element will be available after the CAS latency (CL). The CAS
Latency is defined as CLmrs * tCK + tWCK2CKPIN + tWCK2CK + tWCK2DQO, where CLmrs is the number of
clock cycles programed in MR0, tWCK2CKPIN is the phase offset between WCK and CK at the pins when
phase aligned at phase detector, tWCK2CK is the alignment error between WCK and CK at the GDDR5
SGRAM phase detector, and tWCK2DQO is the WCK to DQ/DBI#/EDC offset as measured at the DRAM
pins

[doktor83]

Just wanted to ask did anybody managed to get over 31+ mhs, but i got my answer before asking

[nerdralph]

You have to loosen it on the DRAM, too - you're loosening the tCL on the ASIC, but not the DRAM, throwing them off.

Interesting.  So the memory controller (or driver) isn't smart enough to take tCL from SEQ_CAS_TIMING and use same value for MR0 Cas Latency?
edit: I don't even understand how this would work at all.  If the controller is expecting the data 22 cycles after the read, but MR0 is programmed for 21, then wouldn't that cause a 100% error rate?

It actually seems to have a tolerance of one value up or down before it stops working entirely.

So I need to update MC_SEQ_MISC1, offset 54 in the hex string of the strap (offset 27 in bytes).  Are the 3 hex chars at offset 55-57 the 12 bits for MR0, or is that MR1 and MR0 is 59-61?
I know I could figure it out by comparing different straps and seeing how the bits map to the register values, but since you seem to have already figured it out...

[Eliovp]

Just wanted to ask did anybody managed to get over 31+ mhs, but i got my answer before asking

That's rather easy, but keeping it there and not setting insanely high clocks, that's the interesting part.

+ i would take a perfectly fine tuned setup with a very low power consumption over high speed any day.

I almost hit 1000h on a 480 8G (XMR) but i prefer 850 stable and very low power consumption.

Greetings!

[laik2]

You have to loosen it on the DRAM, too - you're loosening the tCL on the ASIC, but not the DRAM, throwing them off.

Interesting.  So the memory controller (or driver) isn't smart enough to take tCL from SEQ_CAS_TIMING and use same value for MR0 Cas Latency?
edit: I don't even understand how this would work at all.  If the controller is expecting the data 22 cycles after the read, but MR0 is programmed for 21, then wouldn't that cause a 100% error rate?

It actually seems to have a tolerance of one value up or down before it stops working entirely.

So I need to update MC_SEQ_MISC1, offset 54 in the hex string of the strap (offset 27 in bytes).  Are the 3 hex chars at offset 55-57 the 12 bits for MR0, or is that MR1 and MR0 is 59-61?
I know I could figure it out by comparing different straps and seeing how the bits map to the register values, but since you seem to have already figured it out...

Original Samsung 4G ( your particular GPU ) 1625
555000000000000022CC1C00CE596B44D0570F1531CB2409004AE700 [ 0B03 | 1420 ] 7A8900A003000000170F2E36922A3217

--> MC_SEQ_MISC1
 -- MR0
    WL = 3,  CL = 22,  TM = 0,  WR = 23,  BA0 = 0,  BA1 = 0,  BA2 = 0,  BA3 = 0
 -- MR1
    DS = 0,  DT = 1,  ADR = 1,  CAL = 0,  PLL = 0,  RDBI = 0,  WDBI = 0,  ABI = 0,
    RES = 0,  BA0 = 0,  BA1 = 1,  BA2 = 0,  BA3 = 0

Original Samsung 4G 1750
777000000000000022CC1C0010626C49D0571016B50BD509004AE700 [ 1405 | 1420 ] 7A8900A003000000191131399D2C3617

--> MC_SEQ_MISC1
 -- MR0
    WL = 4,  CL = 23,  TM = 0,  WR = 25,  BA0 = 0,  BA1 = 0,  BA2 = 0,  BA3 = 0
 -- MR1
    DS = 0,  DT = 1,  ADR = 1,  CAL = 0,  PLL = 0,  RDBI = 0,  WDBI = 0,  ABI = 0,
    RES = 0,  BA0 = 0,  BA1 = 1,  BA2 = 0,  BA3 = 0

[Eliovp]

Original Samsung 4G ( your particular GPU ) 1625
555000000000000022CC1C00CE596B44D0570F1531CB2409004AE700 [ 0B03 | 1420 ] 7A8900A003000000170F2E36922A3217

--> MC_SEQ_MISC1
 -- MR0
    WL = 3,  CL = 22,  TM = 0,  WR = 23,  BA0 = 0,  BA1 = 0,  BA2 = 0,  BA3 = 0
 -- MR1
    DS = 0,  DT = 1,  ADR = 1,  CAL = 0,  PLL = 0,  RDBI = 0,  WDBI = 0,  ABI = 0,
    RES = 0,  BA0 = 0,  BA1 = 1,  BA2 = 0,  BA3 = 0

Original Samsung 4G 1750
777000000000000022CC1C0010626C49D0571016B50BD509004AE700 [ 1405 | 1420 ] 7A8900A003000000191131399D2C3617

--> MC_SEQ_MISC1
 -- MR0
    WL = 4,  CL = 23,  TM = 0,  WR = 25,  BA0 = 0,  BA1 = 0,  BA2 = 0,  BA3 = 0
 -- MR1
    DS = 0,  DT = 1,  ADR = 1,  CAL = 0,  PLL = 0,  RDBI = 0,  WDBI = 0,  ABI = 0,
    RES = 0,  BA0 = 0,  BA1 = 1,  BA2 = 0,  BA3 = 0

Bingo!

[kemo6600]

 
seriously guys , leave aside cherry picked cards and post something that can run for at least 48 hours with 5/6 similar cards all running exactly same clocks and hashing at similar speed .

[lpedretti]

seriously guys , leave aside cherry picked cards and post something that can run for at least 48 hours with 5/6 similar cards all running exactly same clocks and hashing at similar speed .

Getting that is the farm administrator work, they're already posting lots of hard to get info

[nerdralph]

So I need to update MC_SEQ_MISC1, offset 54 in the hex string of the strap (offset 27 in bytes).  Are the 3 hex chars at offset 55-57 the 12 bits for MR0, or is that MR1 and MR0 is 59-61?
I know I could figure it out by comparing different straps and seeing how the bits map to the register values, but since you seem to have already figured it out...

Original Samsung 4G ( your particular GPU ) 1625
555000000000000022CC1C00CE596B44D0570F1531CB2409004AE700 [ 0B03 | 1420 ] 7A8900A003000000170F2E36922A3217

--> MC_SEQ_MISC1
 -- MR0
    WL = 3,  CL = 22,  TM = 0,  WR = 23,  BA0 = 0,  BA1 = 0,  BA2 = 0,  BA3 = 0
 -- MR1
    DS = 0,  DT = 1,  ADR = 1,  CAL = 0,  PLL = 0,  RDBI = 0,  WDBI = 0,  ABI = 0,
    RES = 0,  BA0 = 0,  BA1 = 1,  BA2 = 0,  BA3 = 0

Original Samsung 4G 1750
777000000000000022CC1C0010626C49D0571016B50BD509004AE700 [ 1405 | 1420 ] 7A8900A003000000191131399D2C3617

--> MC_SEQ_MISC1
 -- MR0
    WL = 4,  CL = 23,  TM = 0,  WR = 25,  BA0 = 0,  BA1 = 0,  BA2 = 0,  BA3 = 0
 -- MR1
    DS = 0,  DT = 1,  ADR = 1,  CAL = 0,  PLL = 0,  RDBI = 0,  WDBI = 0,  ABI = 0,
    RES = 0,  BA0 = 0,  BA1 = 1,  BA2 = 0,  BA3 = 0

I think you are off by +1 with the MR0 CAS latency.  SEQ_CAS_TIMING has CL=21(0x15) for the 1625 strap, and CL=22(0x16) for the 1750 strap.

[deadsix]

Kinda OT since this is a RAM Timings thread, but ill ask this anyways :

For Sapphire RX 470 4GB (Ref) cards GPU Core Volt offset is at A992 correct?
Now for the cards with Hynix memory, I find the default 04 which is 4 X 6.25 or +25mv, which seems legit.
But for the cards with Samsung memory, the value at A992 is FF which is -1 X 6.25 or -6.25mv, so something looks off.
Do different memory versions of the card have different default offset values? Or is the location different?

Any help/guidance would be appriciated.

[Eliovp]

Kinda OT since this is a RAM Timings thread, but ill ask this anyways :

For Sapphire RX 470 4GB (Ref) cards GPU Core Volt offset is at A992 correct?
Now for the cards with Hynix memory, I find the default 04 which is 4 X 6.25 or +25mv, which seems legit.
But for the cards with Samsung memory, the value at A992 is FF which is -1 X 6.25 or -6.25mv, so something looks off.
Do different memory versions of the card have different default offset values? Or is the location different?

Any help/guidance would be appriciated.

Seems like the samsung one doesn't have global offset.

Stock roms with global offset have either '03' +18.75mV value or '04' +25mV as VDDC offset.
I've never seen something else, or rather negative offset.. and i've opened up a lot of them ;-) 'But correct me if i'm wrong..'

Greetings.

[Truthchanter]

Are there any publicly available custom memory strap timings for the rx 400 series? (samsung, elpida, or hynix)

[Eliovp]

Are there any publicly available custom memory strap timings for the rx 400 series? (samsung, elpida, or hynix)

I posted a basic mod for Elpida And Hynix a few pages back..

[laik2]

So I need to update MC_SEQ_MISC1, offset 54 in the hex string of the strap (offset 27 in bytes).  Are the 3 hex chars at offset 55-57 the 12 bits for MR0, or is that MR1 and MR0 is 59-61?
I know I could figure it out by comparing different straps and seeing how the bits map to the register values, but since you seem to have already figured it out...

Original Samsung 4G ( your particular GPU ) 1625
555000000000000022CC1C00CE596B44D0570F1531CB2409004AE700 [ 0B03 | 1420 ] 7A8900A003000000170F2E36922A3217

--> MC_SEQ_MISC1
 -- MR0
    WL = 3,  CL = 22,  TM = 0,  WR = 23,  BA0 = 0,  BA1 = 0,  BA2 = 0,  BA3 = 0
 -- MR1
    DS = 0,  DT = 1,  ADR = 1,  CAL = 0,  PLL = 0,  RDBI = 0,  WDBI = 0,  ABI = 0,
    RES = 0,  BA0 = 0,  BA1 = 1,  BA2 = 0,  BA3 = 0

Original Samsung 4G 1750
777000000000000022CC1C0010626C49D0571016B50BD509004AE700 [ 1405 | 1420 ] 7A8900A003000000191131399D2C3617

--> MC_SEQ_MISC1
 -- MR0
    WL = 4,  CL = 23,  TM = 0,  WR = 25,  BA0 = 0,  BA1 = 0,  BA2 = 0,  BA3 = 0
 -- MR1
    DS = 0,  DT = 1,  ADR = 1,  CAL = 0,  PLL = 0,  RDBI = 0,  WDBI = 0,  ABI = 0,
    RES = 0,  BA0 = 0,  BA1 = 1,  BA2 = 0,  BA3 = 0

I think you are off by +1 with the MR0 CAS latency.  SEQ_CAS_TIMING has CL=21(0x15) for the 1625 strap, and CL=22(0x16) for the 1750 strap.

This is the tricky part, that's why the numbers don't fit
 -- MR8
    CLEHF = 1,  WREHF = 1,  RFU = 0,  BA0 = 0,  BA1 = 0,  BA2 = 0,  BA3 = 0

[Truthchanter]

Are there any publicly available custom memory strap timings for the rx 400 series? (samsung, elpida, or hynix)

I posted a basic mod for Elpida And Hynix a few pages back..

Very much appreciated, Thank you!