Custom RAM Timings for GPU's with GDDR5 - DOWNLOAD LINKS - UPDATED

[kilo17]

It really depends on the DPM voltage set. Some gpus have higher DPM state without global vddc offset, for example my last MSI Armor 4G 470 has 1.185V DPM7 voltage, while RX 480 Sapphire with global offset of 04 has default 1.0V+0.25V. Open wattool and it will tell you all

That is a little misleading.  Yes WattTool tells you that info but the voltage at DPM7 (or any other for that matter) is determined by the ASIC Quality and is not "set" by the manufacturer.  Yes, some Sapphire Bios' have the +.25mV offset but if you flip the bios switch the other side usually does not.  

Regardless, the ASIC quality determines the DPM and is not directly set by the manufacturer and it does not matter which manufacturer.  That is easy to see by simply setting a manual value that is to low in place of the code in PBE and then running the GPU at full blast.  If you set the DPM7 to 0.9 it would still pull 1.25 using your example and not 0.9.

Last point, WattTool tells some info but if you want a tool to profile it is much better to use AIDA

[rednoW]

My Samsung strap was posted before, but here it is again:
777000000000000022CC1C00CE615C45C0571016B30CD50900400700140514207A8900A00300000 010103139962C3617

With 2100 mclk I'm getting 29-29.1 with sgminer-gm 5.5.5, kernel 4.10.5 & AMDGPU 16.60.

doesn't work on my power color red dragon rx480 8gm samsung mem.
windows driver crash when start ETH, both 2050 and 2100 mem clock.
works good on 2100 clock with 1750 (1625?) strap from original rom
777000000000000022339D00CECD593980551111AE8A84080048C6006C0014206A8900A00200312 0140F262B88252F15

[laik2]

It really depends on the DPM voltage set. Some gpus have higher DPM state without global vddc offset, for example my last MSI Armor 4G 470 has 1.185V DPM7 voltage, while RX 480 Sapphire with global offset of 04 has default 1.0V+0.25V. Open wattool and it will tell you all

That is a little misleading.  Yes WattTool tells you that info but the voltage at DPM7 (or any other for that matter) is determined by the ASIC Quality and is not "set" by the manufacturer.  Yes, some Sapphire Bios' have the +.25mV offset but if you flip the bios switch the other side usually does not.  

Regardless, the ASIC quality determines the DPM and is not directly set by the manufacturer and it does not matter which manufacturer.  That is easy to see by simply setting a manual value that is to low in place of the code in PBE and then running the GPU at full blast.  If you set the DPM7 to 0.9 it would still pull 1.25 using your example and not 0.9.

Last point, WattTool tells some info but if you want a tool to profile it is much better to use AIDA

Thank you, that sounds absolutely correct! I didn't know( I confess ) that DPM voltage is determined by ASIC quality(much to learn, obviously). That sure clarifies all.

[kilo17]

It really depends on the DPM voltage set. Some gpus have higher DPM state without global vddc offset, for example my last MSI Armor 4G 470 has 1.185V DPM7 voltage, while RX 480 Sapphire with global offset of 04 has default 1.0V+0.25V. Open wattool and it will tell you all

That is a little misleading.  Yes WattTool tells you that info but the voltage at DPM7 (or any other for that matter) is determined by the ASIC Quality and is not "set" by the manufacturer.  Yes, some Sapphire Bios' have the +.25mV offset but if you flip the bios switch the other side usually does not.  

Regardless, the ASIC quality determines the DPM and is not directly set by the manufacturer and it does not matter which manufacturer.  That is easy to see by simply setting a manual value that is to low in place of the code in PBE and then running the GPU at full blast.  If you set the DPM7 to 0.9 it would still pull 1.25 using your example and not 0.9.

Last point, WattTool tells some info but if you want a tool to profile it is much better to use AIDA

Thank you, that sounds absolutely correct! I didn't know( I confess ) that DPM voltage is determined by ASIC quality(much to learn, obviously). That sure clarifies all.

You are very welcome.  BTW- take a look a AIDA - you can print off the actual voltage at each DPM for each individual GPU - it can give you all kinds of great info in addition to that

[laik2]

It really depends on the DPM voltage set. Some gpus have higher DPM state without global vddc offset, for example my last MSI Armor 4G 470 has 1.185V DPM7 voltage, while RX 480 Sapphire with global offset of 04 has default 1.0V+0.25V. Open wattool and it will tell you all

That is a little misleading.  Yes WattTool tells you that info but the voltage at DPM7 (or any other for that matter) is determined by the ASIC Quality and is not "set" by the manufacturer.  Yes, some Sapphire Bios' have the +.25mV offset but if you flip the bios switch the other side usually does not.  

Regardless, the ASIC quality determines the DPM and is not directly set by the manufacturer and it does not matter which manufacturer.  That is easy to see by simply setting a manual value that is to low in place of the code in PBE and then running the GPU at full blast.  If you set the DPM7 to 0.9 it would still pull 1.25 using your example and not 0.9.

Last point, WattTool tells some info but if you want a tool to profile it is much better to use AIDA

Thank you, that sounds absolutely correct! I didn't know( I confess ) that DPM voltage is determined by ASIC quality(much to learn, obviously). That sure clarifies all.

You are very welcome.  BTW- take a look a AIDA - you can print off the actual voltage at each DPM for each individual GPU - it can give you all kinds of great info in addition to that

It will be a bit difficult I rarely use windows and if I do it is for 1 GPu only. I will
later see on my hynix the output of aida indeed.

[nerdralph]

Tried 1200/2100 on my Samsung 480 - 30.47MH/s; doesn't matter if I use 4.10 or 4.11rc3.

Thanks for the info; saved me the trouble of testing 4.11.

As for the speed, is that with your Polaris-tuned kernel or stock sgminer-gm 5.5.5?  I still can't get over 29.3 at 1212/2100 (same speed as 1167/2100).
The card is capable of >30, since I get ~30.1 from Claymore 8.1 (1167/2100).

[nerdralph]

My Samsung strap was posted before, but here it is again:
777000000000000022CC1C00CE615C45C0571016B30CD50900400700140514207A8900A00300000 010103139962C3617

With 2100 mclk I'm getting 29-29.1 with sgminer-gm 5.5.5, kernel 4.10.5 & AMDGPU 16.60.

doesn't work on my power color red dragon rx480 8gm samsung mem.
windows driver crash when start ETH, both 2050 and 2100 mem clock.
works good on 2100 clock with 1750 (1625?) strap from original rom
777000000000000022339D00CECD593980551111AE8A84080048C6006C0014206A8900A00200312 0140F262B88252F15

My strap is for K4G4.  Likely different mode registers than your 8G Samsung.

[nerdralph]

Tried 1200/2100 on my Samsung 480 - 30.47MH/s; doesn't matter if I use 4.10 or 4.11rc3.

Thanks for the info; saved me the trouble of testing 4.11.

As for the speed, is that with your Polaris-tuned kernel or stock sgminer-gm 5.5.5?  I still can't get over 29.3 at 1212/2100 (same speed as 1167/2100).
The card is capable of >30, since I get ~30.1 from Claymore 8.1 (1167/2100).

Does over 30 on both. Timings are pretty good, though.

I'm using worksize 192, gpu-threads 2, and xi1024.  You using anything different?

[nerdralph]

I just figured out ohgodadecode has the wrong structure for MISC_TIMING.  Here's a Hynix 1625 strap that shows it: 999000000000000022559D0010DE7B4480551312B78C450A004C0601750414206A8900A00200312 018112D34A42A3816

Here's how I think it should be:

Code:

typedef struct _SEQ_MISC_TIMING_FORMAT
{
    uint32_t TRP_WRA : 7;
    uint32_t TRP_RDA : 7;
    uint32_t TRP : 6;
    uint32_t TRFC : 9;
    uint32_t Pad0 : 3;
} SEQ_MISC_TIMING_FORMAT;

I think the way it was defined is probably correct for R9 series cards, not Rx.

[laik2]

I just figured out ohgodadecode has the wrong structure for MISC_TIMING.  Here's a Hynix 1625 strap that shows it: 999000000000000022559D0010DE7B4480551312B78C450A004C0601750414206A8900A00200312 018112D34A42A3816

Here's how I think it should be:

Code:

typedef struct _SEQ_MISC_TIMING_FORMAT
{
    uint32_t TRP_WRA : 7;
    uint32_t TRP_RDA : 7;
    uint32_t TRP : 6;
    uint32_t TRFC : 9;
    uint32_t Pad0 : 3;
} SEQ_MISC_TIMING_FORMAT;

I think the way it was defined is probably correct for R9 series cards, not Rx.

Here's the correct structure, it was stated earlier in niko2004x's post.
RX

struct {
        uint32_t trp_wra : 7 ;
        uint32_t trp_rda : 6 ;
        uint32_t m1Pad0  : 1 ;
        uint32_t trp     : 5 ;
        uint32_t m1Pad1  : 1 ;
        uint32_t trfc    : 9 ;
        uint32_t m1Pad2  : 3 ;
} mc_seq_misc_timing;

R9

struct {
        uint32_t trp_wra : 6 ;
        uint32_t m1Pad0  : 2 ;
        uint32_t trp_rda : 6 ;
        uint32_t m1Pad1  : 1 ;
        uint32_t trp     : 5 ;
        uint32_t trfc    : 9 ;
        uint32_t m1Pad2  : 3 ;
} mc_seq_misc_timing;

[rednoW]

My Samsung strap was posted before, but here it is again:
777000000000000022CC1C00CE615C45C0571016B30CD50900400700140514207A8900A00300000 010103139962C3617

With 2100 mclk I'm getting 29-29.1 with sgminer-gm 5.5.5, kernel 4.10.5 & AMDGPU 16.60.

doesn't work on my power color red dragon rx480 8gm samsung mem.
windows driver crash when start ETH, both 2050 and 2100 mem clock.
works good on 2100 clock with 1750 (1625?) strap from original rom
777000000000000022339D00CECD593980551111AE8A84080048C6006C0014206A8900A00200312 0140F262B88252F15

My strap is for K4G4.  Likely different mode registers than your 8G Samsung.

thanks for the answer!
Any hint for 8G samsung? My card has no mem cooling so I need some good timings for 2050-2100 range.

[Eliovp]

My Samsung strap was posted before, but here it is again:
777000000000000022CC1C00CE615C45C0571016B30CD50900400700140514207A8900A00300000 010103139962C3617

With 2100 mclk I'm getting 29-29.1 with sgminer-gm 5.5.5, kernel 4.10.5 & AMDGPU 16.60.

doesn't work on my power color red dragon rx480 8gm samsung mem.
windows driver crash when start ETH, both 2050 and 2100 mem clock.
works good on 2100 clock with 1750 (1625?) strap from original rom
777000000000000022339D00CECD593980551111AE8A84080048C6006C0014206A8900A00200312 0140F262B88252F15

My strap is for K4G4.  Likely different mode registers than your 8G Samsung.

thanks for the answer!
Any hint for 8G samsung? My card has no mem cooling so I need some good timings for 2050-2100 range.

There is some serious difference in Samsung Modlues, if you're lucky you can have one like i have.

one that easily breaks 34Mh on ETH.. i'm still surprised myself to be honest..

GPU0 - 1220 / 2150
GPU1 - 1180 / 2100
GPU2 - 1220 / 2100
GPU3 - 1220 / 2100
GPU4 - 1220 / 2100
GPU5 - 1220 / 2100



yeah.. strange indeed 

[nerdralph]

I just figured out ohgodadecode has the wrong structure for MISC_TIMING.  Here's a Hynix 1625 strap that shows it: 999000000000000022559D0010DE7B4480551312B78C450A004C0601750414206A8900A00200312 018112D34A42A3816

Here's how I think it should be:

Code:

typedef struct _SEQ_MISC_TIMING_FORMAT
{
    uint32_t TRP_WRA : 7;
    uint32_t TRP_RDA : 7;
    uint32_t TRP : 6;
    uint32_t TRFC : 9;
    uint32_t Pad0 : 3;
} SEQ_MISC_TIMING_FORMAT;

I think the way it was defined is probably correct for R9 series cards, not Rx.

Here's the correct structure, it was stated earlier in niko2004x's post.
RX

struct {
        uint32_t trp_wra : 7 ;
        uint32_t trp_rda : 6 ;
        uint32_t m1Pad0  : 1 ;
        uint32_t trp     : 5 ;
        uint32_t m1Pad1  : 1 ;
        uint32_t trfc    : 9 ;
        uint32_t m1Pad2  : 3 ;
} mc_seq_misc_timing;

R9

struct {
        uint32_t trp_wra : 6 ;
        uint32_t m1Pad0  : 2 ;
        uint32_t trp_rda : 6 ;
        uint32_t m1Pad1  : 1 ;
        uint32_t trp     : 5 ;
        uint32_t trfc    : 9 ;
        uint32_t m1Pad2  : 3 ;
} mc_seq_misc_timing;

I think mine is better.  I think there is really 7 bits for RP_RDA, and 6 for tRP, but none of the existing straps use the highest bit.

[nerdralph]

Any simple suggestions for a Hynix strap:
999000000000000022559D0010DE5B4480551312B74C450A00400601750414206A8900A00200312 010112D34A42A3816

It's based on the 1625 strap, since the 1500 strap wasn't stable for me beyond 1875.  The 1625 is stable at 1950, but slow (barely over 24Mh), and that's after RRD=5, zeroing FAW and 32AW, ACTRD=16.  I also dropped tRP from 22 to 21, but that didn't make a difference in speed.  From work with other straps, I don't think tightening RAS any more will help.  Any quick tips?

[nerdralph]

There is some serious difference in Samsung Modlues, if you're lucky you can have one like i have.

one that easily breaks 34Mh on ETH.. i'm still surprised myself to be honest..

GPU0 - 1220 / 2150
GPU1 - 1180 / 2100
GPU2 - 1220 / 2100
GPU3 - 1220 / 2100
GPU4 - 1220 / 2100
GPU5 - 1220 / 2100



yeah.. strange indeed 

It's impossible to do >34Mh with a 2150 mem clock.  With 2250, maybe, but certainly not at 2150.

[lexele]

It's based on the 1625 strap, since the 1500 strap wasn't stable for me beyond 1875.

That's very strange, I have several rx with hynix and the 1500 strap is the most stable at least up to 2050.

[Truthchanter]

Are there any publicly available custom memory strap timings for the rx 400 series? (samsung, elpida, or hynix)

Here's the Samsung strap I'm currently working on:
777000000000000022CC1C0010625C49D0571016B50BD50900400700140514207A8900A00300000 0191131399D2C3617

It's the 1750 strap with RRD=5, FAW&32AW=0.  It's stable at 2100 on my Sapphire Rx470.  The previous custom strap I tried was based on the 1625 strap, and I would start getting a lot of errors over 2000.  I just started working on it today, so there's more tweaking to do (like trying a lower tRC for RAS).

Nicely done
Lets see the final results.

Small adjustments to your timing based on my experience : 777000000000000022CC1C00CE615C45C0571016B30CD50900400700140514207A8900A00300000 0151031399D2C3617

Thanks! Nice improvement over the regular 1750 strap. Now the question is... will this 1750 samsung strap work with 480s with samsung (and then both 4gb and 8gb?)

If you have one of the first 4G samsung batches, it will work and even improve even more. (because you can unlock those to 8G)
If you have a newer batch of those 4G samsung's, it will most probably run but won't run stable.

Greetings

Why won't it be stable? Would this only be stable for reference cards?

EDIT: after reading for a bit I saw something about it was only for K4G4 (something like this?) which im guessing means theres different samsung memory modules

[nerdralph]

It's based on the 1625 strap, since the 1500 strap wasn't stable for me beyond 1875.

That's very strange, I have several rx with hynix and the 1500 strap is the most stable at least up to 2050.

He's on Samsung - that's why - Hynix/Elpida, usually 1500 is fine.

No, that's my Asus Strix 470 with Hynix.  My Sapphire ref has Samsung.
And I figured out my problem was 32AW.  I thought I had zero'd it but it was still at 8.  With 32AW=0 now it gets ~27.1 instead of ~24.2 at 1950.
999000000000000022559D0010DE5B4480551312B74C450A00400600750414206A8900A00200312 010112D34A42A3816

[niko2004x]

I just figured out ohgodadecode has the wrong structure for MISC_TIMING.  Here's a Hynix 1625 strap that shows it: 999000000000000022559D0010DE7B4480551312B78C450A004C0601750414206A8900A00200312 018112D34A42A3816

Here's how I think it should be:

Code:

typedef struct _SEQ_MISC_TIMING_FORMAT
{
    uint32_t TRP_WRA : 7;
    uint32_t TRP_RDA : 7;
    uint32_t TRP : 6;
    uint32_t TRFC : 9;
    uint32_t Pad0 : 3;
} SEQ_MISC_TIMING_FORMAT;

I think the way it was defined is probably correct for R9 series cards, not Rx.

Here's the correct structure, it was stated earlier in niko2004x's post.
RX

struct {
        uint32_t trp_wra : 7 ;
        uint32_t trp_rda : 6 ;
        uint32_t m1Pad0  : 1 ;
        uint32_t trp     : 5 ;
        uint32_t m1Pad1  : 1 ;
        uint32_t trfc    : 9 ;
        uint32_t m1Pad2  : 3 ;
} mc_seq_misc_timing;

R9

struct {
        uint32_t trp_wra : 6 ;
        uint32_t m1Pad0  : 2 ;
        uint32_t trp_rda : 6 ;
        uint32_t m1Pad1  : 1 ;
        uint32_t trp     : 5 ;
        uint32_t trfc    : 9 ;
        uint32_t m1Pad2  : 3 ;
} mc_seq_misc_timing;

Nice to know we all arrived to the same structures.

I think mine is better.  I think there is really 7 bits for RP_RDA, and 6 for tRP, but none of the existing straps use the highest bit.

Easy to test.
Set RP_RDA and/or TRP to 0 up to the highest bit (set it to 1) for some high mclk strap. Did not check myself if it is 'crash and burn' or working.
About existing straps you are right.
For RX series maximum values in existings straps are RP_RDA=033, TRP=029 in cards with Micron MT51J256M32HF and Elpida EDW4032BABG.

[nerdralph]

It's based on the 1625 strap, since the 1500 strap wasn't stable for me beyond 1875.

That's very strange, I have several rx with hynix and the 1500 strap is the most stable at least up to 2050.

Maybe your cards have better cooling for the RAM?  This is an Asus Strix.  After tuning the 1625 strap, it was stable at ~27.2Mh with a 1950 mem clock.  Now I'm testing 2000.