Modular FPGA Miner Hardware Design Development

[Olaf.Mandel]

I was trying to figure out who did what to each file and when. I looked at the dropbox events view and was... underwhelmed. This is a hopeless clutter of unfiltered text. My questions:

• Is this list guaranteed to remain available in completeness or is there a cutoff (say, everything older than 500 entries gets discarded)?
• Is there a better way to vie this, say contributions by a single person on all directories or everyone who contributed to a given file?

Also: I saw the previous versions feature. Is it guaranteed that all previous versions are stored indefinitely? This might also be important later, so this must be reliable.

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[MountainMan]

Go MIT and stick with the spirit of BitCoin. GPL is demonic.

[Olaf.Mandel]

Go MIT and stick with the spirit of BitCoin. GPL is demonic.

"MIT" as in "MIT license"? Or "MIT spirit"? And do you have specific concerns with GPL and specific advantages you see for a different license? I must admit not having read the bitcoin manifesto (if any such thing exists).

[li_gangyi]

I've looked at some calculations, if we assume the 10A is spread out across all vias and traces, 0.3mm will handle 1/2 an amp safely, most of the pads have 2 traces supplying Vint. I have no idea how well Vint is spread out internally in the die.

To increase tolerances, we can goto a slightly thicker top layer, the only real way to test if we can continue to use 35um is probably to manufacture one test piece.

[TheSeven]

I think there is nothing in the dropbox so far that I would have a copyright on, so far I've only played an advisory role.
Once it comes to FPGA design and firmware this might change. I'd prefer a FOSS license (MIT, BSD, GPL, LGPL, ...) but would also agree on public domain, if you go for that for whatever reason. This also applies to the FPGA-related code that I have produced so far, especially the Modular Python Bitcoin Miner, or the changes to fpgaminer's code (available in his github repository).
Please note that releasing something into the public domain allows anyone to relicense it in whatever way he wants, including commercial licenses.

[O_Shovah]

On the copyright matter

I hate to draw the attention away from technical the discussion, but I think we are heaping up a lot of future legal hassle at the moment:

IANAL, but as far as I know all creative work is automatically copyrighted to the creator. Publishing it (even on something like dropbox) doesn't change that at all. So if we continue like we currently do, in the end we have a design that may contain key components we don't have permission to use! The FOSS community has a lot of experience with this sort of cr*p, so why don't we take a page from them? Our options at the moment are:

• We put everything into the public domain. Everyone with write access to the dropbox folder has to agree to that and it needs to be stated in a prominently visible file on dropbox.
• We transfer copyright to a single entity (say: O_Shovah's real identity). Again: everyone with write access has to agree. Then O_Shovah has to set a license under which we all can use his copyrighted work, preferably stated in a prominently visible file. He can change his mind, later.
• We each explicitly assign copyright to our work (an AUTHORS file seems to work) and we all agree on a license that applies to the work (LICENSE file).

My own feeling is that this is too cool to just "throw away" by putting it into the public domain. On the other hand, no offence O_Shovah, but I would not want to assign copyright to you. My personal preference is to use a GPL license: there are some issues with applying that to hardware designs, but they seem to be minor. And it works perfectly for the software and firmware.

I am not saying that I will stop working on the project if one of the first options is chosen or if it is a different license. But I think we need to agree on this quickly, before even more people and more copyright holders enter here.

You are pointing out an important issue i already had some headake about.

I certainly will not claim ownership for the projects copyright all alone.This would be angainst any principles i had in mind when starting this project.

I did some research on this matter and now strongly consider founding a company with all those of you contributing to this project.All rights for hardware and software would be confered to this entity giving equally shared rights to each participator.I Considered the german legal company form of the "Unternehmergesellschaft(haftungsbeschränkt)". Wich transferes in english to literally "entrepreneur association (Limited private liability)".
It is similar to the british limited but has some advantages in my eyes.  

This way of organising our legal issues would offer the following advantges :

• All rights would be gathered under one central entity
• The conferation of the individual copyrights to the company would save us problems
    in case someday somebody doesn't want to dedicate his copyright to the project anymore
• As each member of the company shares the same amount rights, a democratic deciscion on any matters is possible.
• We may use to a combination of publicating the project as a noncommercial license open for anybody to build for himself and
    also offering these minersystem in a commercial way to anybody not willing or abled to produce this board himself.
• Nobody would be privat financial liable to any actions of the company and it needs 1€ starting capital

There also would be some downturns :

• As a official company we would have to provide all legal responsebilitys bound to that (guarantee on products,customer support,accounting)
• As such we will also have to pay taxes in case we make some profit
• There is a considerable amount of work needed for founding such a company in germany

I therefore would state that this way is the most secure in a legal way. I asume it is easier to control this as it would be bound to national law.

So please give your comment on that.  

[li_gangyi]

GNU GPL is the simplest and most convenient way to go about protecting this collaborative effort.

[O_Shovah]

I've looked at some calculations, if we assume the 10A is spread out across all vias and traces, 0.3mm will handle 1/2 an amp safely, most of the pads have 2 traces supplying Vint. I have no idea how well Vint is spread out internally in the die.

To increase tolerances, we can goto a slightly thicker top layer, the only real way to test if we can continue to use 35um is probably to manufacture one test piece.

So will you do that test piece for the power supply or shall somebody else do this ?

[Olaf.Mandel]

I must say: I wasn't interested in joining or starting a company (no clue how my employer would feel about that!). For a software project, this is strictly not necessary, just define a license for what you publish and keep track of who owns copyright to what.

I see the point for a hardware development: the prototypes are expensive, and you only get good prices if you pool many orders. For my own part: I just want to get a workable design and possibly not have to sell organs to pay for a small number of boards  

For the purposes of the development effort, these are two separate issues, though: we can assign a license to the designs without having to go to the hassle of incorporating ourselves. The prototypes may even be doable by enthusiasts with deeper pockets than the rest. The mass order requires a company. That needs not be founded by us, though: Seeed Studio is for this sort of thing.

As for license preferences: I would be happy with many of the OSI approved licenses, but GPLv3+ or maybe GPLv2+ would be my preferences.

[senseless]

Does anyone have any data on the LX150 hash power in the real world? I've been hearing wild figures on the forum and IRC from 60mhash/s to 200mhash/s? I was told yesterday that in ISE he (irc user) was playing around and was pretty easily able to obtain an estimated >150mhash/s on the LX150. In another thread someone is saying it would take 9,000$ to make a spartan 6 LX150 board with 1.2ghash/s. Yet I'm finding processor online in bulk for less than 160$ a pop. Which information is real, which is not?

I was wondering if anyone had a dev board they were playing with? If so, what model? The only one I was able to find online was a monster 995$ 4x pci-e card with a ton more features than are needed. It also happened to be out of stock.

[TheSeven]

Does anyone have any data on the LX150 hash power in the real world? I've been hearing wild figures on the forum and IRC from 60mhash/s to 200mhash/s? I was told yesterday that in ISE he (irc user) was playing around and was pretty easily able to obtain an estimated >150mhash/s on the LX150. In another thread someone is saying it would take 9,000$ to make a spartan 6 LX150 board with 1.2ghash/s. Yet I'm finding processor online in bulk for less than 160$ a pop. Which information is real, which is not?

Who was playing around with it? I'd like to contact that guy to avoid duplicating effort
$9000 is certainly way off, but you should also consider the cost of board production, power supply components, and higher prices if you order lower quantities. If you include the cost of design and prototyping respins, $9000 might be close for the first couple of boards. Once the design has been polished I'd think $2000 for 1.2ghash/s might be possible.

[li_gangyi]

I've looked at some calculations, if we assume the 10A is spread out across all vias and traces, 0.3mm will handle 1/2 an amp safely, most of the pads have 2 traces supplying Vint. I have no idea how well Vint is spread out internally in the die.

To increase tolerances, we can goto a slightly thicker top layer, the only real way to test if we can continue to use 35um is probably to manufacture one test piece.

So will you do that test piece for the power supply or shall somebody else do this ?

The main purpose of using the LMZ modules is so that we wouldn't have to do this, I have real life experience with these modules already, and I know they work as advertised, if anyone still wants to make a test PSU, I can ship out some LMZ modules for free to cut down on costs (this are like $15 a pop), eval kits are also available if you just wanna see how well they work.

I propose we route out the rest of the board, make a test batch of PCBs and then I can populate the board with say 1 FPGA to cut down on costs, and then ship them out to software devs who can then figure out what to do with the MCU and FPGA coding. Right now I'm not too worried about the hardware design, I can see active development, but no software dev has stepped up to offer help just yet (or maybe I'm just missing their posts). I'm no good with MSP430s just yet, so I can't help here.

[grid]

I was wondering if anyone had a dev board they were playing with? If so, what model? The only one I was able to find online was a monster 995$ 4x pci-e card with a ton more features than are needed. It also happened to be out of stock.

As for dev boards, the $995 is probably the "Avnet Spartan-6 LX150T Development Kit" (http://goo.gl/S8oHN). This is a LX-150T board (note the T). The upside is that includes the ISE Logic Edition software, node locked to the LX-150T device. Normally the unlocked ISE Logic costs ~$3000

The cheapest board that I found at $750 is this:
https://i.imgur.com/uNDK3.jpg
The Opal Kelly EM6010-LX150. USB 2.0, externally powered, and with a LX-150 (no T). http://goo.gl/LbCWu

It doesn't include an ISE LE license though, so unless you already own one (I certainly don't) you won't be a happy customer.

For volume orders (50+), the price of the EM6010-LX150is $649,99. Another price reference point for us perhaps. Still way above the design target cost for the Modular FPGA Miner.

[senseless]

Who was playing around with it? I'd like to contact that guy to avoid duplicating effort
$9000 is certainly way off, but you should also consider the cost of board production, power supply components, and higher prices if you order lower quantities. If you include the cost of design and prototyping respins, $9000 might be close for the first couple of boards. Once the design has been polished I'd think $2000 for 1.2ghash/s might be possible.

Which guy? The one thread is here. The user is ArtForz in post #30

Pusle was the one telling me of his 150mhash/s in ISE. He said the design wasn't complete and that it should be possible to pump out much more than that. He (or someone) said that FPGAMiner was able to achieve 190mhash/s on the LX150. But I haven't really been able to find any posts from FPGAMiner stating this.

I've been cramming a lot of information RE bitcoin and FPGA for the past week. So it's all still kind of jumbled in my brain.

By my calculation

16 LX150 chips on a x1 pci-e card = 3Ghash/s
16 Chips = 2480$ (at web advertised prices, should be possible to get it for less)
PCB FAB, PSU, ETC estimated that it couldn't cost much more than 250$ per board with a large order.
So, 3Ghash/s for roughly 2730$ (probably less). About 1.09Mhash/s per $ which is more cost effective than a 6990 currently (not to mention the 300 watts of electricity you'll save per GPU you replace).

From what I understand the biggest downside of the LX150 is that it's hard to roll 1.5 engines per chip due to design issues. Again, from my calculations (which are probably wrong in some way). The LX150 could do 3 partial engines using 120K of 150K LU and generate 3hash per 2 cycles. With real world values of around 250mhash/s per chip.

I've got an EE in the family but i'm not savvy to this stuff myself. I was planning on financing the building of some FPGA boards but i'm finding it hard to get accurate figures. Hence why I need a dev board so I can just find out for myself.

It doesn't include an ISE LE license though, so unless you already own one (I certainly don't) you won't be a happy customer.

Thanks for that, looks like a perfect dev board.

What do those licenses cost?

Where do I get an ISE license? From xilinx directly? Avnet?

[O_Shovah]

I've looked at some calculations, if we assume the 10A is spread out across all vias and traces, 0.3mm will handle 1/2 an amp safely, most of the pads have 2 traces supplying Vint. I have no idea how well Vint is spread out internally in the die.

To increase tolerances, we can goto a slightly thicker top layer, the only real way to test if we can continue to use 35um is probably to manufacture one test piece.

So will you do that test piece for the power supply or shall somebody else do this ?

The main purpose of using the LMZ modules is so that we wouldn't have to do this, I have real life experience with these modules already, and I know they work as advertised, if anyone still wants to make a test PSU, I can ship out some LMZ modules for free to cut down on costs (this are like $15 a pop), eval kits are also available if you just wanna see how well they work.

I propose we route out the rest of the board, make a test batch of PCBs and then I can populate the board with say 1 FPGA to cut down on costs, and then ship them out to software devs who can then figure out what to do with the MCU and FPGA coding. Right now I'm not too worried about the hardware design, I can see active development, but no software dev has stepped up to offer help just yet (or maybe I'm just missing their posts). I'm no good with MSP430s just yet, so I can't help here.

If you say so the power supply will certainly do its job.
Bahnfire offered his help a while ago regarding progamming MSP an FPGA and for the FPGa binary we may come back at TheSeven and others so this should be possible to solve.

What do those licenses cost?

Where do I get an ISE license? From xilinx directly? Avnet?

You need the ISE suite for coding and compiling binaris for the FPGA.I remember it to be~2000$ a year so its far form being feasible for me.
They are provided both by Xilinx directly and by Avnet.

I must say: I wasn't interested in joining or starting a company (no clue how my employer would feel about that!). For a software project, this is strictly not necessary, just define a license for what you publish and keep track of who owns copyright to what.

I see the point for a hardware development: the prototypes are expensive, and you only get good prices if you pool many orders. For my own part: I just want to get a workable design and possibly not have to sell organs to pay for a small number of boards  

For the purposes of the development effort, these are two separate issues, though: we can assign a license to the designs without having to go to the hassle of incorporating ourselves. The prototypes may even be doable by enthusiasts with deeper pockets than the rest. The mass order requires a company. That needs not be founded by us, though: Seeed Studio is for this sort of thing.

As for license preferences: I would be happy with many of the OSI approved licenses, but GPLv3+ or maybe GPLv2+ would be my preferences.

So i see we are moving towards a GPL licensing, im ok with  that. The founding a company was just a idea i would have assigned the most security but never mind.

I have just three questions left regarding this licensing type;

As far as i know the GPL doesn't restrict the use to noncommercial use. So there is the option of any company selling out idea for profit as long as the also forward the license including the original authors.

I know the GPL just for software products. Is it this unprobhlematic to directly transfere it to hardware ?

As you proposed we should start a file defining who has generated wich part of the project so we mai define copyright later.

I dont want to sound greedy here but as the copyright only covers hard- and software i would like to have a way to credit all participants like TheSeven, others and me who just participated in a advisory or organisational role.

[bahnfire]

Uploaded new FPGA section of board to dropbox.



Changes compared to last time:

• Changed all unused pins to GND, pull HSWAPEN high for floating pins during configuration
• Use 4 layers
• Added *.dru file for pcbcart service
• Assign one layer each for the different signals:
  
  • 1: GND
  • 2: VCCIO
  • 15: VCCAUX
  • 16: VCCINT
• Placed smallest caps on the backside
• Compactified the board: 83x28mm²

Still to do:

• Get rid of separate VCCAUX and VCCIO as suggested by li_gangyi?
• Are the buses ok like that (all wires on top of each other)?
• Check everything.
• Write a summary of the *.dru.
• Further compactify the resistors (are all needed?) and largest caps..

I would change the unused pins to either be jumpered to GND or leave open with a testpoint/pad. This way you do not design yourself into a hole/corner.

[bahnfire]

Really? The current still needs to go to the top layer and the pads. There the trace width is 0.3mm only! Admittedly, the traces are short (for VCCint at least). But wouldn't you want a bit more copper for these traces? And for GND, I had no choice but to use rather long traces around the centre of the FPGA.

Agree - but this can be taken care of by using a directed pour and many vias. I will need to gain access to the dropbox to check the FPGA routing, but you normall do not want to have long traces from the FPGA balls - you would just use a slight offset and a via to the GND layer.

[Olaf.Mandel]

[...]
I would change the unused pins to either be jumpered to GND or leave open with a testpoint/pad. This way you do not design yourself into a hole/corner.

I don't quite get what you meant here: each pad to a testpoint? Forget it, not in 4 layers with that trace width. All pads to one one testpoint? What is the point? And then you risk having floating inputs with no driver on the signal at all.

Really? The current still needs to go to the top layer and the pads. There the trace width is 0.3mm only! Admittedly, the traces are short (for VCCint at least). But wouldn't you want a bit more copper for these traces? And for GND, I had no choice but to use rather long traces around the centre of the FPGA.

Agree - but this can be taken care of by using a directed pour and many vias. I will need to gain access to the dropbox to check the FPGA routing, but you normall do not want to have long traces from the FPGA balls - you would just use a slight offset and a via to the GND layer.

There are no vias for GND: it's the top layer. There is just no space for the polygon around the centre of the FPGA, so the GND traces get relatively long.

So Dropbox access means not only write access but even read access? Then how did I manage to add the picture? Or is this just security by obscurity, where you have to guess at the URL?

[Olaf.Mandel]

So Dropbox access means not only write access but even read access? Then how did I manage to add the picture? Or is this just security by obscurity, where you have to guess at the URL?

I get it: you don't see the picture I posted unless you are logged in to Dropbox (yes, there is a picture).

@O_Shovah: I was expecting to share the design with everyone, not only the people who contact you. Can you open read access to everyone?

[O_Shovah]

So Dropbox access means not only write access but even read access? Then how did I manage to add the picture? Or is this just security by obscurity, where you have to guess at the URL?

I get it: you don't see the picture I posted unless you are logged in to Dropbox (yes, there is a picture).

@O_Shovah: I was expecting to share the design with everyone, not only the people who contact you. Can you open read access to everyone?

I m sorry.I m afraid this is not possible. When i grant someone access to the folder he has read, write and delete rights to all files.
I personally think a public acess would give the risk of someone not participating spoiling the content(i allready made such experinces).
I allready do a backup every evening.

There is a way to get the files to a public folder with only read access, but in that case you'd need to link every single file and syncronise them manually.

I m working on another solution at the moment. Maybe i can setup an exchange system on one of my servers.