Modular FPGA Miner Hardware Design Development

[inh]

Something I've been mulling over is that the current design wouldn't be much use for anything other than bitcoin. Using SPI as the sole data bus is very limiting in terms of bandwidth. Granted, I still have a lot of research to do, but I think we should consider exposing more of the I/O lines both on the DIMM connector and an the FPGA's themselves. We can still use SPI for communication, but if the FPGA hardware was ever to be re-purposed, it would be great to have 32-64 data lines interconnecting everything that can be used as a super fast data bus. It requires a bit of redesign now but should allow MUCH greater flexibility in software in the future.

Thoughts?

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[O_Shovah]

Well wich BUS standart different from SPI would you propose for gaining more bandwith?

I am still not comfortable with trying to redesign the current setup to a lot more universallity without having a working design at all.

@ daphreak

We already considered the ethernet capability of the setup. But we resceduled it to be implemented in a future succesor to the motherboard.
We thought of using an ARM cortex to do this. But i would also appreciate any proposal for a different IC if you have some experience.

So i woul be glad to have you join our development.



So maybe we should redisscus some parts of the current setup. Specifically:

- Bus System (higher bandwith ?)

- System purpose ( different applications than bitcoin ?)

   
 
 

[daphreak]

@O_Shovah

The part I was talking about is a Cortex M3 from NXP. Looks like we independently arrived at the same conclusion

I am still not comfortable with trying to redesign the current setup to a lot more universallity without having a working design at all.

You mention the "current design". Is it in a repo somewhere? I'd like to take a peek...

As for a bus: you could just connect a bunch of unused pins on the DIMM connectors to each slot and reserve them for future use. That way the motherboard is more universal and any existing card designs can just not connect to those pins.

[inh]

As for a bus: you could just connect a bunch of unused pins on the DIMM connectors to each slot and reserve them for future use. That way the motherboard is more universal and any existing card designs can just not connect to those pins.

Yes exactly. It would just be a parallel data bus. Lots of I/O lines that go between FPGAs and to the DIMM connector. I think 64 should be sufficient? As for system purpose, I think it makes more sense to spend a little more time to make the hardware more general purpose. Yes we could easily make a bitcoin specific cad but with the significant amount of money involved to do this is would really be nice if it was possible for the hardware to have another use outside of bitcoin. I defer to copacobana

[O_Shovah]

@ daphreak

K so we see the same ARM technology for that purpose so far.

Reagarding the Layouts. We share a dropboxfolder and use eagle to create the layouts.
Please pm me your email adress so i may add you to the folder so you can have a look on the layouts and make improvements. 


Reagarding the free I/O lines;  We were supposed to use a DIMM 240 Pin connector.
This should provide the bus connection to the motherboard and the power supply with the 12V rails as you might have read.
( The molex and barrel connectors were meant for standalone purpose or for future applications with more FPGA's an higher currents)
There already has been a huge disscussion if the number of pinns used for the current is sufficient or not.
So if we strip away another 60 of them for the bigger bus we might run into trouble there at least with this connector.   

So basically i may be ok with a more general purpose setup if it is granted that it does not dealy the development by a large margin.
Remember: We are currently 4 maximum 5 people working part time on this project and a too big amount of work ,and therefore time dealy, will make us fail against any other comercial or other solution.
We are not the only ones working on FPGA's now afther all.   

[daphreak]

PM sent.

I will look at the existing design so I can understand the plan for the pinout of these cards better. Sounds like my earlier assumptions that there would be lots of spare IO were wrong.

In the mean time, I think I am going to make a Spartan-6 LX4 (QFP) design with just JTAG and some IO brought out to headers. Basically I want a cheap Spartan-6 to throw some bits at on JTAG. I will probably make 1 or 2 for myself because I don't have a dev board for anything in this series. If everything goes smoothly I should have more accurate price figures by the end of the week but I'm thinking <$30 for it completed. If anyone wants one PM me so I can figure out how many I am going to make.

[O_Shovah]

My MSP 430 devboard just got here.
Got the SPI code running so far.

And just another thougt why im angainst generalising the board design for other applications than bitcoin.
As far as i see all other devboards that are also meant for other applications not only feature high bandwith databuses alike PCIe,
but also locate a lot of high speed memory like DDR 2 or 3 on the board.
The need for additional high speed memory would make our price bill burst up.
And i'm not the one who is going to implement the SPD DDR control logic on the board ( 480 pins...).

[ngzhang]

Too tired these days, go to sleep after this pic.

[O_Shovah]

Nice to see you making such huge progress ngzhang.

Seems your outrunning us in development.

How do you intend to go on with this board ?

Will you share some details or is it not to be published or inbound to our project ?

 

[rph]

Wow. Respect. 

[ngzhang]

Nice to see you making such huge progress ngzhang.

Seems your outrunning us in development.

How do you intend to go on with this board ?

Will you share some details or is it not to be published or inbound to our project ?

 

There are full of bugs on this board. now. But it could work and mining @ 100MHs/each FPGA based on Mokamk's code.
I'm thinking over is or isn't to keep the DIMM golden finger. It really make a high cost on PCB manufacture(50%+ cost). And some other electrical modifications are needed. All these things will be done in 2 weeks, and we will see the 2nd generation.
On the other side, our mining code on it is still under development, maybe release in 2 weeks. It will be like to reach a higher performance.
After these work , BEFORE commercial release of this board, all schematic of this board and mining code of standard performance  will post on this forum.

[O_Shovah]

Hi ngzhang

I would even prefere information about your current " buggy" version over waiting for some weeks.

As you will be aware we  in this thread are highly in need for some feedback and second views onto the hardware side.

So i would appreciate it if you could give us some more details.

[ngzhang]

Hi ngzhang

I would even prefere information about your current " buggy" version over waiting for some weeks.

As you will be aware we  in this thread are highly in need for some feedback and second views onto the hardware side.

So i would appreciate it if you could give us some more details.

Here is the final structure chart.



You know there are competitors. So the detail schematics WILL release a few weeks later.

[newMeat1]

What's up with those squiggly traces, ngzhang? Never seen that before

[kjj]

What's up with those squiggly traces, ngzhang? Never seen that before

Usually, those are used to equalize the lengths of lines used for high speed busses.  Unequal lengths = unequal delays.  Unequal delays =

[ngzhang]

What's up with those squiggly traces, ngzhang? Never seen that before

usually, high speed signal are organized in differential pairs, and these pair groups are in (approx.) same length. So "squiggly traces" is a method to guarantee the length.
You can find them in most high speed designs, maybe on your motherboard or GPU cards.

[makomk]

usually, high speed signal are organized in differential pairs, and these pair groups are in (approx.) same length. So "squiggly traces" is a method to guarantee the length.
You can find them in most high speed designs, maybe on your motherboard or GPU cards.

I take it each of those pairs of lines is connected to an associated pair of differential pins on one of the FPGAs then? That sounds like it could make the boards rather more versatile.

[ngzhang]

usually, high speed signal are organized in differential pairs, and these pair groups are in (approx.) same length. So "squiggly traces" is a method to guarantee the length.
You can find them in most high speed designs, maybe on your motherboard or GPU cards.

I take it each of those pairs of lines is connected to an associated pair of differential pins on one of the FPGAs then? That sounds like it could make the boards rather more versatile.

Certainly. The DIMM has 22 pairs on each FPGA. (44 total) And another 10 pairs each FPGA on the top.(20 total, using a tyco connector).
also 8LEDs and 8 DIP switchs.

[Entropia]

Hi guys. What's up with this development? Nothing has happened in a few weeks, is it dead?

ngzhang: Your miner board is very interesting! Do you have any real-world performance data? Is the board stable? What's the current consumption on the FPGAs? I'm looking forward to the schematics and other files on that board.

[O_Shovah]

Hi,

Basically its still up and running. But as i see it, the crew has reduced itself to me alone.
And im struggeling to programm the MSP (still learning on microcontroller programming).

So the advance is minimal but present.Therefore any help is appreciated.