[ANN] Bitfury is looking for alpha-testers of first chips! FREE MONEY HERE!

[tytus]

Congratulations Bitfury!  

I should be #6 on the waiting list  ; please send samples to me so I can tinker with them

I think I said this before, but I work for the #2 supplier of chip packaging solutions in the world.   I have a Russian translator, and 1-2 Electrical Engineers on hand to help find improvements.

I can probably find resources to help get this thing going faster.

The current chips are in 7x7 QFN48 package and the die is 3.78x3.78. We are trying to find ways to reduce the inductance on (length of) the package bonds and going to a 6x6 package is an option. Another option would be to create a multi chip package or a chip scale package that would add more capacitance closer to the die. Your ideas on that would be welcome.

We will compile a list of tester early next week.

[1715466486]

1715466486

[1715466486]

1715466486

[Anonymailer]

I'd like to get on the tester list too if that's all right, maybe try to get a pi-mac setup working with MacMiner.

[Adano]

Watching. I'd like to see some results from independent testers. May be they can squeeze out more Gh/s from this chip than it's creator.

[intron]

Got bitfury's SPI code working, needed some porting to the smaller
ARM processor, and the ASIC responded nicely. Voltage was adjusted
to 0V64, yielding a current of 1 A. Clock was measured, 116 Mc.

bitfury's testvectors were applied to the ASIC and 100 vectors
gave 145 results, not unlike the result bitfury himself got.

The level shifter in the original schematic works just fine,
so I guess there is no need to fall back to analog pass logic
tricks:) To be safe core power was applied first, then IOVDD.
This was done manually, will be automated in a later design.

intron | c-scape

[intron]

Picture of the FXLP34P5X 1V8 to 3V3 level shifter performance:

http://imgur.com/9bII5tc

Blue trace is the 1V8 signal coming from the bitfury ASIC,
the yellow one is the 3V3 signal going to the ARM processor.
Nice, crisp signals, only a small output delay can be seen.

So no worries here...

intron

[bitfury]

Got bitfury's SPI code working, needed some porting to the smaller
ARM processor, and the ASIC responded nicely. Voltage was adjusted
to 0V64, yielding a current of 1 A. Clock was measured, 116 Mc.

bitfury's testvectors were applied to the ASIC and 100 vectors
gave 145 results, not unlike the result bitfury himself got.

The level shifter in the original schematic works just fine,
so I guess there is no need to fall back to analog pass logic
tricks:) To be safe core power was applied first, then IOVDD.
This was done manually, will be automated in a later design.

intron | c-scape

145 results are all that exists there (not all vectors has answers) - there's 756 cores out of 1024 possible values ;-) so not whole range is scanned.

116 Mhz is making theoretical Gh/s like 116*756/65 = 1365 Mh/s = 1.36 Gh/s :-) Not bad :-) 0.468 W / Gh/s :-)

You can try to increase/decrease voltage - frequency follows voltage automatically.

Also you can switch to external oscillator and check for max frequency - this is what I haven't researched yet.

However - if you get less than 145 results for specified test vector -- this means that some cores are failing at specified frequency ==> less coefficient of performance (COP) - so you should derate real gh/s that you'll get from chip.

[Rampion]

Can't write comments on bitbet.us site... It would be great if they're copy this as well in comments... Sent payouts:

http://bitbet.us/bet/450/bitfurys-asic-will-work-with-power-1/

DATE (2013-06-19 02:08:28) FOR BLOCKCHAIN LOOKUPS:

BET   OUTGOING WALLET                    PAID AMOUNT (WIN)

0.1   1CvadbWnVotoUhrrepxEGqESakmuqHtwnE 0.2
1.0   1NxPnXyN4XmxjysUxLXVXgNGFhYCEGFASV 1.9
10.0  19d6exSEyAPDXLLe3W3ucexpVXUABFeFsy 18.6
1.0   1HP9pTD9ueGYnkEA7Wj7D4SBCesTxXVsNb 1.9
0.044 1GnK5jZxzhFnKCu2yu89XP2JKvBME1em6A 0.1
5.0   16dQP7Nr1irruUTAbiiwYgNB7jQ8NpEVQ3 9.3
1.0   1DEVgggHwKngXf6YSn8ZNBvESTzCDiQWE2 1.9
0.002 1MoaWWXfSFWv6wYpKJEQiRjkmn8gHKBieK 0.1
0.052 19XHbghMRS9HhvWMoKhW8zKFYBSLVz69gB 0.1
4.0   1FzPgqnBrkBZanZwHaAmnd5wRxeDarwr9b 7.4
0.5   1CUanrri8gqXnU8e6bP2Tq8j2DSeBt5Tym 0.9
27.0  1MXf4cFD7EETFQEqD7QdLHbJeGVZfLnbaV 50.2
1.0   1DUv9KXp5CVaEdjvwg5GRUEZ5AhPVy8mnV 1.9
1.5   17xHzsvibCp9SKHParBaHVNZ5yykcjiRTk 2.8
0.05  13ZCqhVuvGL5RqF8WhUdiSFKDScZLZ7Jcz 0.1
0.01  1JCKtVk5W2LVsJiSHGXAcHeRMbZW6RXDAf 0.1
6     13X6T4iGWNHwPstvda7J1XDHbdiugio3j9 11.2

+1 impressive
 
It is too bad you don't sell your products to the rest of the world though... you allow lucky Russian citizens to charge huge mark ups for customers wanting to buy your product in the rest of the world. If they are going to ship worldwide for a profit, why not charge more and ship worldwide yourselves?

I would have bought some units, but honestly I didn't want to order through some sketchy Jr. member. I trust you Bitfury, but not some random person that is reselling your units for profit...

This.

[intron]

Latest test was done to maximize performance, while
keeping chip temperature below 50 degrees C. A small
heatsink was mounted on the bottom of the PCB, and
cooled with a fan to control the temperature.

Internal oscillator set to slow mode, using { 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0x3F, 0x00 } configuration, which
is slightly faster than bitfury's example code.

Vcore at 0.835 Volts, resulting in 2.5A current (2.1W). Clock
frequency of 230 MHz. Instead of bitfury's test vectors, a
test was done with 2048 more or less random vectors.
Based on 756 cores, a yield of 1512 valid hashes would be
expected, but 1511 were found, so COP is very close to 1.

Net hash rate would be almost 2.7 GH/sec @ 0.8W/GH.

With one extra clock bit, core clock increased, but COP
ropped to 0.94, resulting in lower net hash rate.

[dwdoc]

Google translation of a russian webpost from today:

http://translate.google.com/translate?sl=ru&tl=en&js=n&prev=_t&hl=en&ie=UTF-8&u=http%3A%2F%2Fhabrahabr.ru%2Fpost%2F184506%2F

[bitfury]

Latest test was done to maximize performance, while
keeping chip temperature below 50 degrees C. A small
heatsink was mounted on the bottom of the PCB, and
cooled with a fan to control the temperature.

Internal oscillator set to slow mode, using { 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0x3F, 0x00 } configuration, which
is slightly faster than bitfury's example code.

Vcore at 0.835 Volts, resulting in 2.5A current (2.1W). Clock
frequency of 230 MHz. Instead of bitfury's test vectors, a
test was done with 2048 more or less random vectors.
Based on 756 cores, a yield of 1512 valid hashes would be
expected, but 1511 were found, so COP is very close to 1.

Net hash rate would be almost 2.7 GH/sec @ 0.8W/GH.

With one extra clock bit, core clock increased, but COP
ropped to 0.94, resulting in lower net hash rate.

http://imgur.com/g7UTw6V

Great results! Thanks! Hopefully tomorrow Leszek will send more chips, and we'll know more data!

But take care of power noise.

[intron]

Latest test was done to maximize performance, while
keeping chip temperature below 50 degrees C. A small
heatsink was mounted on the bottom of the PCB, and
cooled with a fan to control the temperature.

Internal oscillator set to slow mode, using { 0xFF, 0xFF,
0xFF, 0xFF, 0xFF, 0xFF, 0x3F, 0x00 } configuration, which
is slightly faster than bitfury's example code.

Vcore at 0.835 Volts, resulting in 2.5A current (2.1W). Clock
frequency of 230 MHz. Instead of bitfury's test vectors, a
test was done with 2048 more or less random vectors.
Based on 756 cores, a yield of 1512 valid hashes would be
expected, but 1511 were found, so COP is very close to 1.

Net hash rate would be almost 2.7 GH/sec @ 0.8W/GH.

With one extra clock bit, core clock increased, but COP
ropped to 0.94, resulting in lower net hash rate.

http://imgur.com/g7UTw6V

Great results! Thanks! Hopefully tomorrow Leszek will send more chips, and we'll know more data!

But take care of power noise.

We still need to find out how to chain the SPI bus. The
bitfury S-HASH mining board layout is ready, waiting for
funds to get it etched. Leszek is working on this. When
this board arrives we finally can put 16 bitfury's to work
simultaneously:)

intron

[intron]

Normally, IOREF is set with a restistor divider to half
IOVDD (normally 1V8). To make the board simpler, IOREF
was connected to core voltage.



Core voltage was adjusted between 0V59 and 0V83 V and operation
of the chips remained normal.

Leszek/bitfury, can this be done on the miner board also?
Reduces the wiring a bit.

intron

[bitfury]

Normally, IOREF is set with a restistor divider to half
IOVDD (normally 1V8). To make the board simpler, IOREF
was connected to core voltage.

http://imgur.com/QZYoGDQ

Core voltage was adjusted between 0V59 and 0V83 V and operation
of the chips remained normal.

Leszek/bitfury, can this be done on the miner board also?
Reduces the wiring a bit.

intron

Yes. This is why IOREF pin is there (near VDD . If you don't use external clock and spi is slow enough (you don not worry about width distortion) - it will work  just perfectly. But when you slice CMOS signals not exactly at 50% level - then - you would encounter slight width distortion caused by sampling differences.

[intron]

Normally, IOREF is set with a restistor divider to half
IOVDD (normally 1V8). To make the board simpler, IOREF
was connected to core voltage.

http://imgur.com/QZYoGDQ

Core voltage was adjusted between 0V59 and 0V83 V and operation
of the chips remained normal.

Leszek/bitfury, can this be done on the miner board also?
Reduces the wiring a bit.

intron

Yes. This is why IOREF pin is there (near VDD . If you don't use external clock and spi is slow enough (you don not worry about width distortion) - it will work  just perfectly. But when you slice CMOS signals not exactly at 50% level - then - you would encounter slight width distortion caused by sampling differences.

So what to do on the mining board: connect IOREF to Vcore or connect IOREF to IOVDD/2?

intron

[tytus]

Normally, IOREF is set with a restistor divider to half
IOVDD (normally 1V8). To make the board simpler, IOREF
was connected to core voltage.

http://imgur.com/QZYoGDQ

Core voltage was adjusted between 0V59 and 0V83 V and operation
of the chips remained normal.

Leszek/bitfury, can this be done on the miner board also?
Reduces the wiring a bit.

intron

Yes. This is why IOREF pin is there (near VDD . If you don't use external clock and spi is slow enough (you don not worry about width distortion) - it will work  just perfectly. But when you slice CMOS signals not exactly at 50% level - then - you would encounter slight width distortion caused by sampling differences.

So what to do on the mining board: connect IOREF to Vcore or connect IOREF to IOVDD/2?

intron

VDD => lets's forget the IOREF line.

[intron]

VDD => lets's forget the IOREF line.

Nice. It's in the schematic already:)

[Felipeo]

really nice to see how the work boils, and everything is going in the right direction 

[intron]

Development mining board 'bitfury S-HASH' is underway:



From this the low-cost mining boards will be derived.
We get it working hopefully soon and try to learn from it.

intron

[Foofighter]

really nice to see how the work boils, and everything is going in the right direction 

+1

[MRKLYE]

I'm interested in 16-20 chips for testing and R&D here in Canada.
Would love a USB single or double board made up. Maybe I can reverse engineer one off the s-hash!
What do you need for shipping costs?