giorgiomassa
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August 30, 2013, 01:19:05 PM |
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Is there anything special to be done to end a bitfury chain?
I'm trying to make one single chip being detected and used by cgminer but while it does solve test vectors with spitest, cgminer nor chainminer are able to use it for mining.
I'm assuming that outclk, outsck, outmiso, outmosi don't have to be connected for a single chip system...
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ssi
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August 30, 2013, 03:59:32 PM |
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Is there anything special to be done to end a bitfury chain?
I'm trying to make one single chip being detected and used by cgminer but while it does solve test vectors with spitest, cgminer nor chainminer are able to use it for mining.
I'm assuming that outclk, outsck, outmiso, outmosi don't have to be connected for a single chip system...
Where is this "spitest"? Is it a pre-written test vector program that I missed in here somewhere? That'd help me tremendously getting a beaglebone bitfury port
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18xEDfc7y1Nzm2kmLvwYq56xwwEz4Fdh6
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cscape
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August 30, 2013, 04:03:33 PM |
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Happy with your c-scape product ? Consider a tip: 16X2FWVRz6UzPWsu4WjKBMJatR7UvyKzcy
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ssi
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August 30, 2013, 04:13:03 PM |
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Awesome, I missed that... thanks cscape
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18xEDfc7y1Nzm2kmLvwYq56xwwEz4Fdh6
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gingernuts
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August 30, 2013, 07:30:55 PM |
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In an SPI chain of chips, does the OUTMOSI go back to the host, or does the return data get routed back down the chain to INMISO?
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ssi
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August 30, 2013, 09:29:27 PM |
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In an SPI chain of chips, does the OUTMOSI go back to the host, or does the return data get routed back down the chain to INMISO?
The latter. output port of the final chip doesn't need to go anywhere.
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18xEDfc7y1Nzm2kmLvwYq56xwwEz4Fdh6
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AtomSea
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So sexy, it hurts.
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September 01, 2013, 02:15:27 AM |
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My first DIY bitfury solar miner. The box under panel contains RasPi and custom single chip mining board (its heatsink is sticking out of the box). The chip's core powered directly from the panel (Uoc=1.15V, Isc=5.5A, Ucore=0.87V), and RasPi powered from the cord. After the first half hour of mining I observed unusual high hashrate (>3Gh/s) of single bitfury chip. Just to mention I was unable to get more than 2.9Gh/s from this chip when it was powered from buck converter (0.85-0.9V). You can follow hashrate graph of my solar miner at http://eligius.st/~wizkid057/newstats/userstats.php/15YLSMUNxNZpWjjkego2fNJw78BgigZiiuNice!!!
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chirale
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September 01, 2013, 02:24:48 AM |
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My first DIY bitfury solar miner. The box under panel contains RasPi and custom single chip mining board (its heatsink is sticking out of the box). The chip's core powered directly from the panel (Uoc=1.15V, Isc=5.5A, Ucore=0.87V), and RasPi powered from the cord. After the first half hour of mining I observed unusual high hashrate (>3Gh/s) of single bitfury chip. Just to mention I was unable to get more than 2.9Gh/s from this chip when it was powered from buck converter (0.85-0.9V). You can follow hashrate graph of my solar miner at http://eligius.st/~wizkid057/newstats/userstats.php/15YLSMUNxNZpWjjkego2fNJw78BgigZiiuFantastic!! Green economy! Nice!!!
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LaserHorse
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September 02, 2013, 06:12:52 AM |
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enter the 'BitCranky' … speed:491 noncerate[GH/s]:20.043 (2.227/chip) hashrate[GH/s]:21.002 good:1400 errors:27 spi-errors:0 miso-errors:0 jobs:274 coreVDD = 0.84V
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intron
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- electronics design|embedded software|verilog -
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September 02, 2013, 06:20:17 AM |
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enter the 'BitCranky' …
speed:491 noncerate[GH/s]:20.043 (2.227/chip) hashrate[GH/s]:21.002 good:1400 errors:27 spi-errors:0 miso-errors:0 jobs:274
coreVDD = 0.84V
Nice!! intron
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cscape
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September 02, 2013, 06:20:57 AM |
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Very nice, very colorful!
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Happy with your c-scape product ? Consider a tip: 16X2FWVRz6UzPWsu4WjKBMJatR7UvyKzcy
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kaerf
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September 02, 2013, 06:21:33 AM |
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lol! that is awesome!
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LaserHorse
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September 02, 2013, 10:31:26 AM |
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thnx - build process was fun, gave me some ideas for a couple of new modular designs. Just wish I had prettier perfboard - beige/green not my ideal color scheme "Grrrrrr … more chips, more pi!", said the bitcranky
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kakobrekla
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September 02, 2013, 10:58:08 AM |
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enter the 'BitCranky' … speed:491 noncerate[GH/s]:20.043 (2.227/chip) hashrate[GH/s]:21.002 good:1400 errors:27 spi-errors:0 miso-errors:0 jobs:274 coreVDD = 0.84V Very nice! Heres ours:
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Fiyasko
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Okey Dokey Lokey
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September 02, 2013, 01:35:24 PM |
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I am absolutely loving the look of these Bitfury powered ASIC's, and even more so I love that the ASIC's were despensed to the public rather than just one building bi•fury assembled and with heatsink: It's hashing test vectors now, more to come. intron Note: the push button, pin header and Molex connector are for firmware debugging only, will be removed later. This is exactly what I was hoping to see, SUPER BLOCK ERUPTERS!
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intron
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- electronics design|embedded software|verilog -
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September 02, 2013, 09:32:53 PM |
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Mounted S-HASH on a heatsink and got it hashing: Vcore = 0V8 Some bitfury ASIC stats: stats 1 min: 2.97 3.13 3.21 3.21 2.47 2.55 2.31 3.05 3.71 2.64 2.88 2.06 3.30 2.72 2.55 3.13 5 min: 3.33 2.98 2.90 2.57 2.72 2.64 2.57 3.03 3.16 2.52 2.84 2.55 2.88 2.79 2.72 3.07 15 min: 3.23 3.14 2.91 2.51 2.82 2.60 2.71 2.79 3.02 2.68 2.71 2.58 2.93 2.96 2.96 3.03 intron PS: I'm hashing with 41.2 GH/s FYI.
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LaserHorse
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September 02, 2013, 09:52:01 PM |
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Mounted S-HASH on a heatsink and got it hashing:
[…]
Vcore = 0V8
Some bitfury ASIC stats:
stats 1 min: 2.97 3.13 3.21 3.21 2.47 2.55 2.31 3.05 3.71 2.64 2.88 2.06 3.30 2.72 2.55 3.13 5 min: 3.33 2.98 2.90 2.57 2.72 2.64 2.57 3.03 3.16 2.52 2.84 2.55 2.88 2.79 2.72 3.07 15 min: 3.23 3.14 2.91 2.51 2.82 2.60 2.71 2.79 3.02 2.68 2.71 2.58 2.93 2.96 2.96 3.03
intron
PS: I'm hashing with 41.2 GH/s FYI.
Whoah - 40GH @ 0V8 and so few caps! What prompted the removal of the 8-cap clusters between each quad of chips? Not necessary?
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intron
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- electronics design|embedded software|verilog -
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September 02, 2013, 09:57:54 PM |
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Mounted S-HASH on a heatsink and got it hashing:
[…]
Vcore = 0V8
Some bitfury ASIC stats:
stats 1 min: 2.97 3.13 3.21 3.21 2.47 2.55 2.31 3.05 3.71 2.64 2.88 2.06 3.30 2.72 2.55 3.13 5 min: 3.33 2.98 2.90 2.57 2.72 2.64 2.57 3.03 3.16 2.52 2.84 2.55 2.88 2.79 2.72 3.07 15 min: 3.23 3.14 2.91 2.51 2.82 2.60 2.71 2.79 3.02 2.68 2.71 2.58 2.93 2.96 2.96 3.03
intron
PS: I'm hashing with 41.2 GH/s FYI.
Whoah - 40GH @ 0V8 and so few caps! What prompted the removal of the 8-cap clusters between each quad of chips? Not necessary? They are rather expensive, so we decided to remove them. But the power supply is now behaving a bit odd, so in rev 3 some of the caps will be back:) If you look closely you see a stack of caps just behind the DC/DC converter. They were added to add some more stability to the output voltage. intron
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LaserHorse
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September 02, 2013, 11:12:26 PM |
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They are rather expensive, so we decided to remove them. But the power supply is now behaving a bit odd, so in rev 3 some of the caps will be back:)
If you look closely you see a stack of caps just behind the DC/DC converter. They were added to add some more stability to the output voltage.
intron
indeed - I was a bit shocked @ the price of poscaps. 13 of them are hiding on the underside of my DC/DC converter. Calculating Rtune & Ctune via the GigaTLynx datasheet was vague to say the least …
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intron
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- electronics design|embedded software|verilog -
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September 03, 2013, 12:23:22 AM |
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Attached a Pt100 sensor and did some measurements. Not getting very hot, only 38.5 oC. Time to start OC-ing I guess:) intron
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