[ANN] Bitfury is looking for alpha-testers of first chips! FREE MONEY HERE!

[BR0KK]

Hey just to clarify, Is ssi's design of what appears to be a pci-e 1x card with a backplane a pci card that you can stick into regular motherboards? Or is it a rack style "blade"

It's a blade... not going to work in a regular motherboard   There will be backplanes and chassis for them.

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But it would make a nice pcie 1x card

Great work!

[1715632349]

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[cscape]

The internal clock has some jitter, which reduces the setup/hold windows inside the chip. Theoretically, with a stable external clock you should be able to go a little bit faster. But is it worth the effort ? The internal clock has an advantage that you can tune it per chip.

[gingernuts]

OK, so it sounds like everybody things internal clocks are the way to go - fair enough!

Does anyone know what the lead time is on single chips? I want to roll a board, but it probably doesn't make sense to fully populate it at 80E per chip - if the price really is being reviewed weekly, I'm half tempted to wait for the boards to come back from the fab before I pay for some samples...

[ssi]

OK, so it sounds like everybody things internal clocks are the way to go - fair enough!

Does anyone know what the lead time is on single chips? I want to roll a board, but it probably doesn't make sense to fully populate it at 80E per chip - if the price really is being reviewed weekly, I'm half tempted to wait for the boards to come back from the fab before I pay for some samples...

The first batch of chips I ordered was shipped within 1 day.  I've ordered two more batches since then, one order thursday, one order saturday, and neither has even been acknowledged yet.

[Tyger]

Can someone confirm that ioref is not drawing any power, or if it is how much.

[intron]

Logged the hash rate of the sixteen individual
bitfurys on the S-HASH board:



Some binning of the ASICs before assembly
might be a good idea...

intron

[intron]

Can someone confirm that ioref is not drawing any power, or if it is how much.

On the H-board, IOREF is connected with Vcore.
And Vcore should be a high Amp net anyways,
so current consumption of IOREF is not much of
a concern.

But there are no numbers on current consumption
as far as I know.

intron

[ssi]

Some binning of the ASICs before assembly
might be a good idea...

intron

You get that binner spun yet?   I'd love your layout if you're interested in making it public

[ssi]

Can someone confirm that ioref is not drawing any power, or if it is how much.

On the M-board, IOREF is connected with Vcore.
And Vcore should be a high Amp net anyways,
so current consumption of IOREF is not much of
a concern.

But there are no numbers on current consumption
as far as I know.

intron

What about Vddio consumption?  I've been going overboard with current capacity on io, but it'd be nice to know the actual number.

[intron]

What about Vddio consumption?  I've been going overboard with current capacity on io, but it'd be nice to know the actual number.

Also no idea. On the M-board a 1V8/4A power supply is
used to supply VDD_IO to up to 16 M-boards. That seems
to work ok.

intron

[cscape]

You get that binner spun yet?   I'd love your layout if you're interested in making it public

The PCB should be ready in a few days.

[intron]

Some binning of the ASICs before assembly
might be a good idea...

intron

You get that binner spun yet?   I'd love your layout if you're interested in making it public

Layout is not the problem, you need a ton of firmware too;)

intron

[ssi]

Some binning of the ASICs before assembly
might be a good idea...

intron

You get that binner spun yet?   I'd love your layout if you're interested in making it public

Layout is not the problem, you need a ton of firmware too;)

intron

point taken

[Tyger]

What about Vddio consumption?  I've been going overboard with current capacity on io, but it'd be nice to know the actual number.

Also no idea. On the M-board a 1V8/4A power supply is
used to supply VDD_IO to up to 16 M-boards. That seems
to work ok.

intron

A ioref pin should not draw any power or very little so thats why im intrested in this.

[Andreoid]

Designed to have a heatsink mounted to the back with airflow; I expect this sucker to require some cooling! 

If you want to overclock them and expect to much heat, please feel welcome to contact us (anfi-tec) for some watercoolers.
Furthermore for a better packing density.

That might be a good option... I'd need a waterblock that's about 100x30mm.

• what do you think will the 12 chips produce in heat/Power consumption in idle?
• and the same with overclocking?
• how many of these miniboards you plan to put on a backplane/rack?
• what distance is planned for the pci-slots (with watercooling you can pack them much closer together than with aircooling)
• are you planing to sell these miniboards?
• cooling from the backside of the board like the avalonchips?

i am sure that we can't use here one waterblock for two boards like we did with bitburner XX waterblock

[ssi]

Designed to have a heatsink mounted to the back with airflow; I expect this sucker to require some cooling! 

If you want to overclock them and expect to much heat, please feel welcome to contact us (anfi-tec) for some watercoolers.
Furthermore for a better packing density.

That might be a good option... I'd need a waterblock that's about 100x30mm.

• what do you think will the 12 chips produce in heat/Power consumption in idle?
• and the same with overclocking?
• how many of these miniboards you plan to put on a backplane/rack?
• what distance is planned for the pci-slots (with watercooling you can pack them much closer together than with aircooling)
• are you planing to sell these miniboards?
• cooling from the backside of the board like the avalonchips?

i am sure that we can't use here one waterblock for two boards like we did with bitburner XX waterblock

12 chips at full rate will produce around 30W.  The 40A regulator probably another 5W.
The bottom of the module has the soldermask masked back to show bare plated copper for good heat transfer.  Yes, cooling from the backside of the board.

Heatsink dimension should be 100x35mm.  I'll get you the mounting hole pattern this evening; they're 2mm mounting holes.

For the backplanes I'm designing now (for aircooling), the slots are 36mm apart.  Here's a render of a 480GH miner on a 16 way backplane:

[ssi]

What about Vddio consumption?  I've been going overboard with current capacity on io, but it'd be nice to know the actual number.

Also no idea. On the M-board a 1V8/4A power supply is
used to supply VDD_IO to up to 16 M-boards. That seems
to work ok.

intron

A ioref pin should not draw any power or very little so thats why im intrested in this.

ioref != vddio

[vs3]

What about Vddio consumption?  I've been going overboard with current capacity on io, but it'd be nice to know the actual number.

Also no idea. On the M-board a 1V8/4A power supply is
used to supply VDD_IO to up to 16 M-boards. That seems
to work ok.

intron

A ioref pin should not draw any power or very little so thats why im intrested in this.

ioref != vddio

IOVDD current consumption should be around 0.25A at 1.8V per chip.
(from what I can tell via google translate - source: https://bitcointalk.org/index.php?topic=242745.msg2964335#msg2964335)

[ssi]

What about Vddio consumption?  I've been going overboard with current capacity on io, but it'd be nice to know the actual number.

Also no idea. On the M-board a 1V8/4A power supply is
used to supply VDD_IO to up to 16 M-boards. That seems
to work ok.

intron

A ioref pin should not draw any power or very little so thats why im intrested in this.

ioref != vddio

IOVDD current consumption should be around 0.25A at 1.8V per chip.
(from what I can tell via google translate - source: https://bitcointalk.org/index.php?topic=242745.msg2964335#msg2964335)

a quarter amp per chip?   If that's accurate, I don't have enough, and neither does intron/cscape... 256 chips would require 64 amps of io current! D:

[vs3]

What about Vddio consumption?  I've been going overboard with current capacity on io, but it'd be nice to know the actual number.

Also no idea. On the M-board a 1V8/4A power supply is
used to supply VDD_IO to up to 16 M-boards. That seems
to work ok.

intron

A ioref pin should not draw any power or very little so thats why im intrested in this.

ioref != vddio

IOVDD current consumption should be around 0.25A at 1.8V per chip.
(from what I can tell via google translate - source: https://bitcointalk.org/index.php?topic=242745.msg2964335#msg2964335)

a quarter amp per chip?   If that's accurate, I don't have enough, and neither does intron/cscape... 256 chips would require 64 amps of io current! D:

yeah, tell me ... I've put a 1.5A regulator on my board and a 1-ohm resistor so that I can measure it more accurately. I'll know for sure next week when I get my boards. I was hoping to be <150mA (so that I can use a much much cheaper 1.8V LDO )