[ANN] Bitfury is looking for alpha-testers of first chips! FREE MONEY HERE!

[intron]

1. INCLK should be tied to power or ground in case if it is not connected to clock generator. Otherwise if it will be floating, especially near half-voltage - it will case spontaneous oscillations.
   Better to feed it with oscillator, but don't feed less than 100 Mhz, or feed MUCH less than 100 Mhz as you can find bad package resonance.

There is no PLL on board? Feeding many chips with
"not less then 100 MHz" over the entire board can
be quite challenging.

intron

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[MrTeal]

Even a 0.5mm pitch QFN isn't that tough to dead bug. This took about 20 minutes and it's a 0.5mm pitch QFN24. Forgive the crappy iPhone photos.



I agree though, properly mounting the chips would be best. There's really no reason not to, other than the turnaround of a week raising the price of a PCB. Even buying a surfboard would be easier.

[stripykitteh]

I've studied the protocol a bit more. It's about as bare-bones as it gets. No return code checks.

So, if I understand correctly, if chaining is 'on' you will always address all the chips in the chain by setting the address to the address of the first chip on the bus. If  chaining is 'off' you set the address to that of the individual chip. If there is a broken chip you can still use the bus up to the point of the broken chip by setting the length parameter accordingly.

It would be good to develop a test suite on top of this that would exercise chains of different lengths - single, double, 4x, etc. Is there a maximum expectation of chain length?

I guess if you don't get a dead chip in your batch you have to sacrifice one to test the test suite.

[innovation]

OK, I have waited with great patience till http://bitbet.us/bet/450/bitfurys-asic-will-work-with-power-1/ went to pending resolution status. It gets more and more interesting.

Right now we had trouble with getting chips "in time" for tests (as we expected to get chips on 30th May and do the test earlier in June). So my friend went to Taiwan to get chips, meanwhile packaging factory tries to push delivery to 13th... We'll work hard to push it back to 10th or 11th as they promised second time. But it depends... More information will be available likely on monday.

So - to speedup testing and provide plausible and trustworthy confirmation of performance I have decided that we will send sample chips to 3-4 persons of this forums with following conditions:

- We will send 10-30 chips (number of chips is that what you could select yourself depending on your custom issues - say if you sure that no problem to get 30 sample chips - we'll send 30). Preliminary specs - each chip would give roughly 5 GH/s performance.
- You will solder AS SOON AS YOU GET chip it using dead-bug style (for later chip make PCBs of course, however if you are eager to run it quicker - dead-bug might be right way) with bypass capacitors underneath and will try to run it, measure power consumption and performance with different voltage modes (sweep from 0.5 V to 0.9 V).
- You will post photos in any case - not depending whether chip works or not, it could be also interesting if you could scrub the top and post photo of its internals (if you could remove AL_RDL layer that would be great).
- You have to understand C programming language and boards like raspberrypi (if not you should team up with programmer) - but that's mandatory, and understand how to deal with quick power-hungry chip (i.e. capacitor bypass selection,  power impedance issues).
- It would be great, but not mandatory, if you have good web of trust to these persons who are running website bitbet.us: http://serajewelks.bitcoin-otc.com/trustgraph.php?source=kakobrekla&dest=mircea_popescu as they do not trust our results much, and it would be nice to give them bulletproof confirmations _IN_TIME_ for bet resolution.
- Reporting during some time how chips behave - whether they all alive and hash good or broke with time passed, and guesses why they break (maybe by sending chip to us so we could unpackage them and scan them to find out failure reason).

Additional requirements:

- Being hacker at least a bit... As we haven't enough time to write documentation, and you'll basically get C-code for raspberry that is capable to communicate, not well-tested. Some half-working miner code. Chip pinout. Maybe verilog code... It's a bonus if you could do debug - in case if chip will not work and you'll find bug - we'll likely just pay additional bonus for that. Don't expect good written documentation of any kind and don't expect that I will be able to spend many hours explaining how to make this job. Likely we'll open separate discussion thread and will discuss issues there.
- You would likely need lab power supply, if you don't have - then prepare 0.6 - 0.9 V power supply with current up to 6 amps, power supply of 1.8 V with current 100-200 mA
- raspberry-pi board or board like that (first software will be designed for it), if other board used - you should know what you do and do it yourself - SPI required.
- maybe you should have to use EXTERNAL clock generator giving 150 - 500 Mhz programmable frequency output.
- it would be great to have at hand 500 - 1000 Mhz oscilloscope, even better to have 10 Ghz oscilloscope to make clock jitter measurements, also it would be even greater to have spectrum analyzer with 4-10 Ghz bandwidth to measure power noise spectral content and debug in case if you have excessive pulsations in power network at certain frequencies by reworking capacitor bypass network to get good performance (however all of that can be skipped if we are lucky enough and have good margins in chip).
- handle chip carefully - as ESD-protection may underperform and may not give 2kV HBM protection for example. This should be met, but we don't know if it is met or not yet.

If candidates will be 3-4 or less - they will get chips, if more - I will collect in PM or in this thread requests to take opportunity with testing, make after 24 hours additional POLL topic, and those who will be elected will get chips. 48 hours after this message I hope everything will be known and settled.

Chips will be sent on 10-11th from Taiwan, if we'll find out how to help our packaging factory to make it happen, but it can be later as well. Anyway it is not only bet issue, but we would like to know about chips performance AS SOON AS POSSIBLE. I think that opportunity to get these hashes earliest would be excellent motivation to execute tests in shortest possible terms.

PS. I've read that someone here is reselling metabank.ru offers with our chips. I would like to clarify - first - neither me nor metabank.ru endorses these resellers. Second - metabank.ru is not taking 'prepayment', its just preorders with 100% refund  just to freeze funds - basically people can just show them bitcoins and keep on their OWN wallets (not moving them). Its mainly purpose is just preliminary evaluation of volumes for next production batch. With other sales, etc - that all will be discussed only AFTER testing. So my advice - don't be crazy and don't buy BS (Edited: this is what I meant - is those crazy sellers for $5k with prepayment and without guarantees, BitCentury seems to be legit and faithful).... But of course you may be lucky and that will happen as advertised - that's your win/loose.

PPS. About further distribution of chips - we have ideas (yet only ideas we'll see how that will happen in reality) - standard instrument "chip futures with real delivery with expiration date MM.YYYY", it would be traded online and actual delivery will be done by tytus (Leszek), and instead of direct contract there will be one single public contract. Then - for small to medium order amounts actual acquisition would be done to multiple locations using intermediaries who will do assembly, certification and will have end-user support for the devices. For bigger quantities it will be possible to get chips directly. I think some of delivery locations will convert "bulk" into smaller amounts for chip deliveries as well. But to grasp overall idea - we'll not multiply headache, but actually spread headache among many many heads, so each will have much less headache to pass and grow to higher volumes. Also there's some technical issues that we're discussing - how to organize it... I would like to deploy fully-featured peer-to-peer real-time exchange as open-source project and invite current web-sites to distribute tickers and handle cash-in/cash-out issues (that's not limited to these futures, but are open for many participating parties as well), but being objected that it's quite complex and not trivial to do in limited time. I hope that if we have enough of luck and chip will work, I'll have enough time to make this actually happen.

SO PLEASE, DON'T BOMBARD ME WITH REQUESTS TO BUY CHIPS, ETC. JUST BE PATIENT.

Can I have this chance? I am a newbie from China.

[MrTeal]

1. INCLK should be tied to power or ground in case if it is not connected to clock generator. Otherwise if it will be floating, especially near half-voltage - it will case spontaneous oscillations.
   Better to feed it with oscillator, but don't feed less than 100 Mhz, or feed MUCH less than 100 Mhz as you can find bad package resonance.

There is no PLL on board? Feeding many chips with
"not less then 100 MHz" over the entire board can
be quite challenging.

intron

I'd agree with this, initial testing on one chip should be fine. I have an Agilent AFG3252 so I'd be limited to a max of 240MHz but I don't imagine I would be able to hit that without without reasonable cooling anyway. Running a 500MHz clock at full speed around a board to multiple chips is a bit of a concern. Did you envision using multiple external PLLs for each group of ASICs?

[americandesi]

Reserved and Observing.!

[nightyj]

Nice work, I am in for testing, pm sent.

[bitfury]

1. INCLK should be tied to power or ground in case if it is not connected to clock generator. Otherwise if it will be floating, especially near half-voltage - it will case spontaneous oscillations.
   Better to feed it with oscillator, but don't feed less than 100 Mhz, or feed MUCH less than 100 Mhz as you can find bad package resonance.

There is no PLL on board? Feeding many chips with
"not less then 100 MHz" over the entire board can
be quite challenging.

intron

There's no PLL on board. There's two kinds of self-running internal oscillators based on programmable delays, but these may fail or give bad performance. It is quite sensitive things. So for testing I left INCLK pin.
Likely it should not be used (INCLK). But OUTCLK likely will be used to test internal oscillator frequency, whether it changes too much or have artifacts.

Putting 500 Mhz isn't big deal if you have good impedance matching. Same is for output. But to chain high speed clock - you have to setup carefully voltage at IOREF pin (even without chain!) so you get duty cycle captured correctly.
Parameters is what I am currently worried.  100 Mhz is even easier. Just have in mind that at such frequencies on short lines on PCB you work likely in LC-mode of transmission line with all of the consequences, maybe even RC-line, depending on its length!

Also don't forget about level shifters - i/O is 1.8 V not 3.3 V (!!!).

[bitfury]

Even a 0.5mm pitch QFN isn't that tough to dead bug. This took about 20 minutes and it's a 0.5mm pitch QFN24. Forgive the crappy iPhone photos.
I agree though, properly mounting the chips would be best. There's really no reason not to, other than the turnaround of a week raising the price of a PCB. Even buying a surfboard would be better (and easier).

EXCELLENT JOB! Now trick is to actually solder together VDD pins and put proper capacitors between GND pad and VDD pads connected. Then solder to central pad THICK wire - interesting how that could be done (as heat sink). Initially I thought that it must be done with hot air after capacitors soldered and chip is held.... wires would be soldered as last step as it would be hard to solder to thermal pad if you have thick wire there.

One of the ways how to do - take thick wire - say 16 sq.mm, solder it from one side thoroughly, cut (remove also insulation if any) - say leave 50mm of wire length... Then - heat wire first while holding it with pliers, then heat chip and wire togeher and connect them. Then you'll have to cool this with air and then spread copper wires and you'll get heatsink.

[MrTeal]

1. INCLK should be tied to power or ground in case if it is not connected to clock generator. Otherwise if it will be floating, especially near half-voltage - it will case spontaneous oscillations.
   Better to feed it with oscillator, but don't feed less than 100 Mhz, or feed MUCH less than 100 Mhz as you can find bad package resonance.

There is no PLL on board? Feeding many chips with
"not less then 100 MHz" over the entire board can
be quite challenging.

intron

There's no PLL on board. There's two kinds of self-running internal oscillators based on programmable delays, but these may fail or give bad performance. It is quite sensitive things. So for testing I left INCLK pin.
Likely it should not be used (INCLK). But OUTCLK likely will be used to test internal oscillator frequency, whether it changes too much or have artifacts.

Putting 500 Mhz isn't big deal if you have good impedance matching. Same is for output. But to chain high speed clock - you have to setup carefully voltage at IOREF pin (even without chain!) so you get duty cycle captured correctly.
Parameters is what I am currently worried.  100 Mhz is even easier. Just have in mind that at such frequencies on short lines on PCB you work likely in LC-mode of transmission line with all of the consequences, maybe even RC-line, depending on its length!

Also don't forget about level shifters - i/O is 1.8 V not 3.3 V (!!!).

Are there any restrictions on IOVDD when trying to run the chip with VDD at 0.5V?

[bitfury]

2 MrTeal: there's amplifier circuitry between core and iO voltage. What I don't know is power-up sequence - should be not important (i.e. no latch up) - but unsure.
So IOVDD can be 1.8V while VDD is 0.5 V -  no problem.

I've studied the protocol a bit more. It's about as bare-bones as it gets. No return code checks.

So, if I understand correctly, if chaining is 'on' you will always address all the chips in the chain by setting the address to the address of the first chip on the bus. If  chaining is 'off' you set the address to that of the individual chip. If there is a broken chip you can still use the bus up to the point of the broken chip by setting the length parameter accordingly.

To understand better - there's component

INPUT ---> [ SPICTRL ] ---> OUTPUT
                      |
                      v
                 INTERNALS

Mesage is routed to internals only when DATA transmission is done - it basically sets address and executes bits programming data on setup addresses.
In case if chip is intermediary - it just propagates DATA from input to output and does not modify internal state, same for prefix instructions, so consider it as programmable SPI switch component.

It would be good to develop a test suite on top of this that would exercise chains of different lengths - single, double, 4x, etc. Is there a maximum expectation of chain length?

depends much on failure rates. Actually SPI has lower probability of failure than say cores - as SPI is made of really big cells, looking more like 180nm using 65nm rules. Say 4 vias duplication on every wire there. Also SPI is small
so overall yield should be good.

I guess if you don't get a dead chip in your batch you have to sacrifice one to test the test suite.

well - it depends on failure actually... how I should take it down...

[MrTeal]

Even a 0.5mm pitch QFN isn't that tough to dead bug. This took about 20 minutes and it's a 0.5mm pitch QFN24. Forgive the crappy iPhone photos.
I agree though, properly mounting the chips would be best. There's really no reason not to, other than the turnaround of a week raising the price of a PCB. Even buying a surfboard would be better (and easier).

EXCELLENT JOB! Now trick is to actually solder together VDD pins and put proper capacitors between GND pad and VDD pads connected. Then solder to central pad THICK wire - interesting how that could be done (as heat sink). Initially I thought that it must be done with hot air after capacitors soldered and chip is held.... wires would be soldered as last step as it would be hard to solder to thermal pad if you have thick wire there.

One of the ways how to do - take thick wire - say 16 sq.mm, solder it from one side thoroughly, cut (remove also insulation if any) - say leave 50mm of wire length... Then - heat wire first while holding it with pliers, then heat chip and wire togeher and connect them. Then you'll have to cool this with air and then spread copper wires and you'll get heatsink.

Yes, with how you laid out the pins it should actually be relatively easy. As you say, just use a bus for Vdd across the entire row of Vdd with a few 0402 capacitors to the thermal pad. You could either use a thick wire to connect Vss, or use an array of pins. I was planning on using maybe 4-6 of the pins from a 2mm header as the ground, since that would give you a decent bit of surface area that you could run a fan across them.

I'm putting together a PCB for testing, but I'll have to see whether it's reasonable to get it fabbed and shipped to me at a reasonable cost by Thursday. What is the max SPI speed supported by the chip?

[nightyj]

You can order experimental pcbs with cooling pads such as http://www.ebay.com/itm/PCB-adapter-for-QFP44-or-QFN44-package-/161025491663?pt=UK_BOI_Electrical_Components_Supplies_ET&hash=item257dde02cf .
I am planing to order my pcbs at the local pcb assembly factory to make accurate testing, cause testing with long wires and no pads under the chips will give a lot different operation results from the real pcb working enviroment.

About the cooling wire that you plan to add solder to the chips pad it is better to be added first cause it will need a lot of heating and can resolder the other wires, once the big wire is soldered it will be even easirer to solder the others cause this wire can also act like stand.

[MrTeal]

You can order experimental pcbs with cooling pads such as http://www.ebay.com/itm/PCB-adapter-for-QFP44-or-QFN44-package-/161025491663?pt=UK_BOI_Electrical_Components_Supplies_ET&hash=item257dde02cf .
I am planing to order my pcbs at the local pcb assembly factory to make accurate testing, cause testing with long wires and no pads under the chips will give a lot different operation results from the real pcb working enviroment.

I'm not so much talking about doing thorough chip testing and trying to see what is possible, I'm looking at what would need to be done on a single chip in order to have results posted by next Friday afternoon. I don't have any QFN/QFP48 ones laying around, so you'd have to make sure you can get them in by Thursday or so.

[bitfury]

Even a 0.5mm pitch QFN isn't that tough to dead bug. This took about 20 minutes and it's a 0.5mm pitch QFN24. Forgive the crappy iPhone photos.
I agree though, properly mounting the chips would be best. There's really no reason not to, other than the turnaround of a week raising the price of a PCB. Even buying a surfboard would be better (and easier).

EXCELLENT JOB! Now trick is to actually solder together VDD pins and put proper capacitors between GND pad and VDD pads connected. Then solder to central pad THICK wire - interesting how that could be done (as heat sink). Initially I thought that it must be done with hot air after capacitors soldered and chip is held.... wires would be soldered as last step as it would be hard to solder to thermal pad if you have thick wire there.

One of the ways how to do - take thick wire - say 16 sq.mm, solder it from one side thoroughly, cut (remove also insulation if any) - say leave 50mm of wire length... Then - heat wire first while holding it with pliers, then heat chip and wire togeher and connect them. Then you'll have to cool this with air and then spread copper wires and you'll get heatsink.

Yes, with how you laid out the pins it should actually be relatively easy. As you say, just use a bus for Vdd across the entire row of Vdd with a few 0402 capacitors to the thermal pad. You could either use a thick wire to connect Vss, or use an array of pins. I was planning on using maybe 4-6 of the pins from a 2mm header as the ground, since that would give you a decent bit of surface area that you could run a fan across them.

Great idea! Yeah - with pin layout - I did layout thinking of strings of chip assembly and did most of redistribution inside of chip, having in mind that for example it could fit on metal-core PCB when you don't have many layers. So wires should be straight there. If everything is wired correctly

I'm putting together a PCB for testing, but I'll have to see whether it's reasonable to get it fabbed and shipped to me at a reasonable cost by Thursday. What is the max SPI speed supported by the chip?

Well - with PCB take care of capacitor impedance. I doubt that thick 2-layer PCB will work better than capacitors you put there. I'll give you model:

1) Internal capacitance is about 50 nF
2) wirebond single VDD wire is about 1.5 - 1.8 nH
3) wirebond to GND is about 0.04 nH

total VDD+GND wirebond inductance is about 0.08 nH
resonant frequency of this internal LC-tank is about 70 Mhz.

Make at least ESL (serial inductance) to capacitors to about the same - of 0.08 nH
If you have 0402 and place it really well - it would have about 0.4 nH inductance - so put at least 5 of them there. But depends on your capacitors actually, they're a bit different.
Then if your power supply is far away (lab power supply) - I would put somewhere there 1 or 2 tantal caps and maybe some 0805 caps. But to calculate actual numbers - err - should do math - for frequencies up to say 100 Mhz here lumped circuit and it is pretty straightforward to calculate by hand using complex amplitudes... not slept too long, unfortunately will not do now :-)
The overall idea of power supply is to get |Z|(w) adequate low value, and rather flat without increasing peaks at specific frequencies that will be excited when chip average consumption changes a bit cycle to cycle (this is what I would like actually to see - how power consumption spectrum looks like). Also beware of parasitic resonances when different caps are placed (C - L - C) - that's why I offered such analysis.

Inside chip there's largest power consumption spike is 200-300 ps current risetime with target of about 8 amps, while average consumption is about 4 Amps for 0.8 V. It's pretty tought. As the more ripple on internal VDD ==> less clock you'll have or at low voltages flip-flops can loss data.

To sum up - I can't say if it will work as expected in say on 2-layer pcb with big homemade vias and large distances between caps and chip it will work as expected. Much more capacitors shall be installed with less efficiency.
Please note that small capacitor works as INDUCTOR at high frequencies... Not as capacitor... it shorts higher frequencies as small INDUCTOR would. INDUCTANCE IS PROPORTIONAL TO CURRENT PATH AREA (!!!). So - having larger distance between planes + larger distance for electrons to flow from your capacitors and they will flow without being happy and will do their job of calculating hashes lazily, so to keep them happy - reduce number of inductors on their way!

[J35st3r]

Dead bug? Plenty of QFN Adapters available with next day delivery. May need to drill out centre to access ground pad though.

[Edit] Oops, just noticed nightyj post above, I should read entire thread before posting,  
Don't buy from ebay though. Use Digikey, RS, Farnell etc.

[MrTeal]

Dead bug? Plenty of QFN Adapters available with next day delivery. May need to drill out centre to access ground pad though.

If you check the pinout, the only ground is the bottom pad. You could use a surfboard and it would be much easier, but you would have to be pretty creative to mount bypass caps close to the pins as there aren't any grounds on the top of the PCB.

[danattacker]

I'm registering my interest as a tester.

I own a Raspberry Pi and understand C.
I do not own a lab power supply. I would have to order parts from Digikey (which takes 2 days for me to get parts from).
I can generate a clock signal up to ~300 MHz (I think) using FPGA DCM.
I only have a 100 MHz DSO.
I have the ability to etch my own PCBs.
I own a soldering and SMD rework station.

Thank you.

[zulunation]

PM sent

[2112]

EXCELLENT JOB! Now trick is to actually solder together VDD pins and put proper capacitors between GND pad and VDD pads connected. Then solder to central pad THICK wire - interesting how that could be done (as heat sink). Initially I thought that it must be done with hot air after capacitors soldered and chip is held.... wires would be soldered as last step as it would be hard to solder to thermal pad if you have thick wire there.

One of the ways how to do - take thick wire - say 16 sq.mm, solder it from one side thoroughly, cut (remove also insulation if any) - say leave 50mm of wire length... Then - heat wire first while holding it with pliers, then heat chip and wire togeher and connect them. Then you'll have to cool this with air and then spread copper wires and you'll get heatsink.

I've seen QFN-packaged parts soldered to the top of a thick brass/copper bolt, e.g. for a 7mm*7mm package use 5mm diameter bolt. That wasn't done for cooling, it was hand-made modification while doing a thermal characterization/calibration of a mixed-signal SoC.

It looked like a high-current diode, but was neither high-current nor high-frequency, just a way to reduce the inherent internal heating of the SoC executing the boot / self-test / calibration program.

Edit: Actually I misremembered, the bolts were made of phosphor bronze. I don't know how easy would be to obtain such parts. They aren't expensive, but are considered "specialty" / "non-stock" / "special order" items.