Project Evil Genius – Custom SHA2-256 Circuits on a FPGA

[DoctorDoom]

e

[goxed]

I will use this thread to update my progress. I will update every once in a while to let people know my progress and how well the circuits are preforming. 

I will be creating custom digital circuits of a SHA2-256 Double Hashers for Bitcoin mining. I have already started on the first stage. The project will be written in Verilog. I chose Verilog, because it has better controls at the gate level than VHDL. I will not be using any C code for the hashing circuits. However I might use C code for the registers and connections to the computer, IE USB plug, and set-up data.

Looking at the Open Source FPGA code, I believe I can make a really good improvement over the Open Source code, which is converted C. I have vast experience in digital design and I have worked on many ASIC projects. However, I have not worked on a FPGA before, but I have worked alongside FPGA programmers to know the major problems that affect FPGAs.

To get more info on my background, go here:
http://www.cryptoextractor.com/crypto/author.html

Depending on the results, three things will happen. If I get really great results, then I would probably make some boards and sell them. If I get good results, I will probably buy old FPGA boards and reprogram them, and mine with them. I might sell some of the re-programmed boards. The last would be if I got OK results. Then I would just release the code as Open Source.

why don't you try developing scrypt mining for LTC for opensource community. There's avery high demand for it IMO.

[Milan77]

I will use this thread to update my progress. I will update every once in a while to let people know my progress and how well the circuits are preforming. 

I will be creating custom digital circuits of a SHA2-256 Double Hashers for Bitcoin mining. I have already started on the first stage. The project will be written in Verilog. I chose Verilog, because it has better controls at the gate level than VHDL. I will not be using any C code for the hashing circuits. However I might use C code for the registers and connections to the computer, IE USB plug, and set-up data.

Looking at the Open Source FPGA code, I believe I can make a really good improvement over the Open Source code, which is converted C. I have vast experience in digital design and I have worked on many ASIC projects. However, I have not worked on a FPGA before, but I have worked alongside FPGA programmers to know the major problems that affect FPGAs.

To get more info on my background, go here:
http://www.cryptoextractor.com/crypto/author.html

Depending on the results, three things will happen. If I get really great results, then I would probably make some boards and sell them. If I get good results, I will probably buy old FPGA boards and reprogram them, and mine with them. I might sell some of the re-programmed boards. The last would be if I got OK results. Then I would just release the code as Open Source.

why don't you try developing scrypt mining for LTC for opensource community. There's avery high demand for it IMO.

+100

[joeventura]

I will use this thread to update my progress. I will update every once in a while to let people know my progress and how well the circuits are preforming. 

I will be creating custom digital circuits of a SHA2-256 Double Hashers for Bitcoin mining. I have already started on the first stage. The project will be written in Verilog. I chose Verilog, because it has better controls at the gate level than VHDL. I will not be using any C code for the hashing circuits. However I might use C code for the registers and connections to the computer, IE USB plug, and set-up data.

Looking at the Open Source FPGA code, I believe I can make a really good improvement over the Open Source code, which is converted C. I have vast experience in digital design and I have worked on many ASIC projects. However, I have not worked on a FPGA before, but I have worked alongside FPGA programmers to know the major problems that affect FPGAs.

To get more info on my background, go here:
http://www.cryptoextractor.com/crypto/author.html

Depending on the results, three things will happen. If I get really great results, then I would probably make some boards and sell them. If I get good results, I will probably buy old FPGA boards and reprogram them, and mine with them. I might sell some of the re-programmed boards. The last would be if I got OK results. Then I would just release the code as Open Source.

What would you define as "really great results"?

[Milan77]

Maybe a good idea will also be implenmentig salted SHA1 algo for Nokia SL3 unlocking by bruteforce method.

[Kuroth]

Watching...

[fpgaminer]

Looking at the Open Source FPGA code, [...], which is converted C.

You mean https://github.com/fpgaminer/Open-Source-FPGA-Bitcoin-Miner?  That's not converted C.

[Zalfrin]

Looking at the Open Source FPGA code, [...], which is converted C.

You mean https://github.com/fpgaminer/Open-Source-FPGA-Bitcoin-Miner?  That's not converted C.

I originally didn’t know that code was converted C or not. I had assumptions that it was converted C, and asked in the past in different threads when I talked about this project. Then I talked to people from this forum, and all of them told me that it was converted C. So I believe it was converted C. I am sorry for calling it Converted C.

It's pretty obvious it's not converted C code, if you are talking about an automated C-to-HDL program. Those spit out garbage code. The Open Source code is human-readable - therefore not machine generated.

Good luck. Personally I doubt there is much performance left on the table by the open source code, but please prove us wrong.

[goxed]

Maybe a good idea will also be implenmentig salted SHA1 algo for Nokia SL3 unlocking by bruteforce method.

Any URL listing the problem? It looks interesting.

[Milan77]

Yes, with pleasure:

http://hashcat.net/wiki/doku.php?id=cracking_sl3

It is pretty good explained.

It is little modified salted SHA1 algo and should be around 5 times faster than algo used for BTC.
For sure it is possible to implement on FPGA. But there is a lot of pro guys with already done solution, not willing to share their work.

Atom (admin and creator of Hashcat and OCLHashcat) is great guy and very skillful programmer, he did a LOT of optimization on crypto algos, maybe he could do even more if someone gets his attention.

[fpgaminer]

I still believe I can make a big performance jump over the code. I will try to get down to the gate level as much as possible and use all the logic there. I have even been looking through the specs and schematics to see how the slices work on the Spartan-6.

It's a lot of fun down there!  It's a shame the Spartan 6 architecture is so limited.  I suggest you take a look at the 7-series FPGAs, like the Kintex or Artix.  The architecture is nicer, and performance is much higher.  For example, I was able to implement a miner using the DSP48E1s on a Kintex.

Also, have you looked at bitfury's code?  He has the most performant code for Spartan-6 LX150 chips, and I would be shocked if anyone beat his record (in MH/s) on that chip.  It's optimized down at the slice level and manually placed.  https://bitcointalk.org/index.php?topic=228677.msg2417706#msg2417706

Unfortunately, or fortunately (depending on how you look at it), FPGA's will never beat ASICs in terms of performance per dollar, or performance per Watt.  So FPGA mining is a curiosity and plan-B sort of thing now.

For sure it is possible to implement on FPGA.

I coded up a quick SL3 cracker about a year ago.  It either ran on my Spartan 6 devkit, or the X6500, I can't recall.  I could probably dump the code to github if people are interested.  I didn't optimize it particularly well, just got it working.

[Milan77]

For sure it is possible to implement on FPGA.

I coded up a quick SL3 cracker about a year ago.  It either ran on my Spartan 6 devkit, or the X6500, I can't recall.  I could probably dump the code to github if people are interested.  I didn't optimize it particularly well, just got it working.

FPGAMINER

Getting SL3 unlock to FPGA miners would give them new life. I do not have much of them but they will be more universal if someone keeps them running SL3.

Also I am not rich, but willing to support job with some BTCs.

[turtle83]

Also, have you looked at bitfury's code?  He has the most performant code for Spartan-6 LX150 chips, and I would be shocked if anyone beat his record (in MH/s) on that chip.  It's optimized down at the slice level and manually placed.  https://bitcointalk.org/index.php?topic=228677.msg2417706#msg2417706

Is there a compiled bitstream compatible with ztex out there?

[polarhei]

I will use this thread to update my progress. I will update every once in a while to let people know my progress and how well the circuits are preforming. 

I will be creating custom digital circuits of a SHA2-256 Double Hashers for Bitcoin mining. I have already started on the first stage. The project will be written in Verilog. I chose Verilog, because it has better controls at the gate level than VHDL. I will not be using any C code for the hashing circuits. However I might use C code for the registers and connections to the computer, IE USB plug, and set-up data.

Looking at the Open Source FPGA code, I believe I can make a really good improvement over the Open Source code, which is converted C. I have vast experience in digital design and I have worked on many ASIC projects. However, I have not worked on a FPGA before, but I have worked alongside FPGA programmers to know the major problems that affect FPGAs.

To get more info on my background, go here:
http://www.cryptoextractor.com/crypto/author.html

Depending on the results, three things will happen. If I get really great results, then I would probably make some boards and sell them. If I get good results, I will probably buy old FPGA boards and reprogram them, and mine with them. I might sell some of the re-programmed boards. The last would be if I got OK results. Then I would just release the code as Open Source.

why don't you try developing scrypt mining for LTC for opensource community. There's avery high demand for it IMO.

Memory is problem. He will

[Milan77]

Great, keep going!

[Magnate]

If this does work you should be able to get twice the engines into one FPGA. There is money in this as there are plenty of FPGAs out there and I'm sure ppl would love to double thier hash rate!!

[sveetsnelda]

I coded up a quick SL3 cracker about a year ago.  It either ran on my Spartan 6 devkit, or the X6500, I can't recall.  I could probably dump the code to github if people are interested.  I didn't optimize it particularly well, just got it working.

I'd also be very interested in a git, and I'd certainly throw a tip your direction.

[BBQKorv]

Only if you were here a year ago, now this is a bit late if not obsolete very soon. I'm hoping the best and I'm very interested to see how well you manage to do with this project.

[southerngentuk]

Watching, good luck with this. 

[goxed]

I had a great night last night for the Evil Genius project. I got my first pre-design partially working in software. The size of the SHA-256 circuit was reduced by 0.52 to 0.37 (not giving out the exact size reduction). The next step is I am going to build a full software implementation in an OpenCL Kernel. I don’t believe the performance of the Kernel will be better than anything out there, because I cannot increase the GPUs hardware and GPUs are not specifically built for SHA-256. It is more of a proof of concept thing. Also, I will still be able to pipeline the work with the smaller design. So every clock cycle, you will get data. After the full implementation, I will see if I can patent the design method. The circuit has 64 stages for one hash, so 128 stages for the double hash.

This is just the first pre-design. I still have some other things I want to try out. But this is very promising. I was very excited last night. I cannot wait to start trying some other things out to see how far I can push the SHA-256 circuit.  

Edit: It should be reduce ‘to’ 0.52-0.37, instead of ‘by’. I am cutting myself short  . So now the circuit is basically half the size or smaller, so the performance increase will be 2x or more.

May I ask did you obtain the size reduction on a HDL module or was it something else?