BFL Monarch update

[Bogart]

They never seem to mention the possibility of the silicon failing testing and needing a respin.

Their 65nm chips needed 2 respins before they were able to ship anything.

Logically 28nm is a good bit harder to get right than 65nm.

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[ralree]

Thanks for posting - I guess we'll see how it goes!

[mruiter]

"unforseen problems and delays can and do happen and we will do our best to alert everyone to them when we encounter them"

I agree, first unforseen problem is you guys bought from BFL. .... Haha i Kill myself....

[superduh]

PSA was released to the public:

HashTrade is the company who bought $1 million worth of products from BFL. buy their contracts at your own risk

[Puppet]

Their 65nm chips needed 2 respins before they were able to ship anything.

Do you have a source for that? Not saying its not true, I just never heard it. For the record, a respin means redoing one or more of the masks in the maskset.
what I read was that they had issues mostly with the chip packaging,  but you can change packaging without redoing the mask, you can even do it with wafers that are already produced (but not yet packaged).

[Vagnavs]

PSA was released to the public:

HashTrade is the company who bought $1 million worth of products from BFL. buy their contracts at your own risk

http://www.hashtrade.com/
appears to be the site

[Puppet]

They suppose to start delivery in Oct 2012.  From October to April they were doing what?  At least 2 respins, IMHO.

Their FPGA took about as long, if not longer to materialize. Yet I doubt they "respun" someone else's FPGA .

BTW, IIRC they received their first silicon (which was wirebonded for testing) in late February or early March. A respin takes 6-8 weeks at least, its basically redoing the tapeout, and waiting for new wafers to be processed, and thats after you diagnosed and fixed the problem. Realistically, more like 10 weeks.  It would have been impossible to do 2 respins in that timeframe. Even one seems impossible.

[Easy2Mine]

Their 65nm chips needed 2 respins before they were able to ship anything.

Do you have a source for that? Not saying its not true, I just never heard it. For the record, a respin means redoing one or more of the masks in the maskset.
what I read was that they had issues mostly with the chip packaging,  but you can change packaging without redoing the mask, you can even do it with wafers that are already produced (but not yet packaged).

Bogart speaks the truth.
From Josh words I count 2 respin, but I suspect 3.
Josh like to exaggerate things and spread news all over the place 24/7.
At one point he was quiet.
The engines didn't work as planned.
Long time no news in this period
They hoped the engines will work at 500 mh/s at a certain power envelop.
It turned out that the engines will max at 250 mh/s with a greater power usage than the final product.
So I suspect another respin here.

Originally they hoped to design a chip with 16 engines running at 500 mh/s each. 16*500mh/s=8Gh/s.
8 chips per single 8*8=64 Gh/s. at less than 1 watt per Gh/s was the plan.
We all know now that they need double the ammount of chips at a greater power envelop.

[smoothie]

Any updates Josh gives always add 9 months to it and that's much more accurate of a timeline. So he says January, try next september.

[Puppet]

Bogart speaks the truth.
From Josh words I count 2 respin, but I suspect 3.
Josh like to exaggerate things and spread news all over the place 24/7.
At one point he was quiet.
The engines didn't work as planned.
Long time no news in this period
They hoped the engines will work at 500 mh/s at a certain power envelop.
It turned out that the engines will max at 250 mh/s with a greater power usage than the final product.
So I suspect another respin here.

Originally they hoped to design a chip with 16 engines running at 500 mh/s each. 16*500mh/s=8Gh/s.
8 chips per single 8*8=64 Gh/s. at less than 1 watt per Gh/s was the plan.
We all know now that they need double the ammount of chips at a greater power envelop.

You may suspect it, but Ive not seen any evidence (what "Josh words" are you referring to?) and your own logic argues against it, since the chips were delivered at 250Mhz, the same speed they observed in first silicon in late February. More over as I argued above, the timing just doesnt leave room for one, much less 3 respins, unless you want believe they received silicon back in 2012 and didnt talk about it.

[Easy2Mine]

Bitfury and Asicminer did it in one time.
Avalon I don't know, but I think also 1 time.
Asicminer and Avalon use older and proven technology.
I have to applaud for Asicminer, they have just slight more than 100k to pull it off.
Bitfury goal is probably 5 Gh/s per chip.
Although they didn't archieve that, the chip works good enough, no need to respin to save time.

[Xian01]

we feel our timeline to begin shipments towards the end of the year is solid."

 Respectfully, experience and history on these forums will clearly illustrate that the only thing that is solid, is the density of their bullshit.

[Easy2Mine]

You can re-read all of Inaba and BFL_Josh posts. I don't have time to search all the messages

[Easy2Mine]

You may suspect it, but Ive not seen any evidence (what "Josh words" are you referring to?) and your own logic argues against it, since the chips were delivered at 250Mhz, the same speed they observed in first silicon in late February. More over as I argued above, the timing just doesnt leave room for one, much less 3 respins, unless you want believe they received silicon back in 2012 and didnt talk about it.

You know how the singles originally suppose to look like?

[Puppet]

You can re-read all of Inaba and BFL_Josh posts. I don't have time to search all the messages

ITs all here:
https://forums.butterflylabs.com/announcements/692-bfl-asic-status-3.html

First hashing around early March as I remembered. No mention of a respin or anything that could be considered a respin. No 8+ week gap either. No time for a respin, let alone 3. Just a long list of fucking up missing design parameters,  packaging, firmware, PCB's, supply chain, software, pretty much everything else you can fuck up. Maybe they did one or several respins for later products, as is often done to improve yields or tweak stuff, but the ones that shipped in April must have been made with the same maskset (ie, no respin) as the one that they published in February/march as their first prototype.  Thus, that is not what caused the delays.

[Bogart]

Their 65nm chips needed 2 respins before they were able to ship anything.

Do you have a source for that? Not saying its not true, I just never heard it. For the record, a respin means redoing one or more of the masks in the maskset.
what I read was that they had issues mostly with the chip packaging,  but you can change packaging without redoing the mask, you can even do it with wafers that are already produced (but not yet packaged).

The first respin would be from their "diffraction issue", incorrectly called a "refraction issue" by Josh in some earlier discussion:

It's kinda hard to dig up the quotes now, and it doesn't help that BFL's forums keep giving me the CloudFlare 504 error.

https://forums.butterflylabs.com/bfl-forum-miscellaneous/690-13-jan-2013-asic-update-discussion-thread-9.html#post10463

https://forums.butterflylabs.com/announcements/251-more-jalapeno-pictures-shipping-update-17-print.html (second post quotes Josh's statement.)

The second being where they claimed to be "adding clock buffers", and at the same time they changed package types:

https://bitcointalk.org/index.php?topic=128019.msg1363605#msg1363605

[Easy2Mine]

Thank you Bogart for digging it up.

[Photon939]

They also did another respin once they had working chips, I'm not sure where they switched but revision A chips couldn't use engine 0 and revision B can. Their stock firmware would actually underclock some of the revB units because they would run at >70GH/s but would overheat badly.

[Puppet]

Their 65nm chips needed 2 respins before they were able to ship anything.

Do you have a source for that? Not saying its not true, I just never heard it. For the record, a respin means redoing one or more of the masks in the maskset.
what I read was that they had issues mostly with the chip packaging,  but you can change packaging without redoing the mask, you can even do it with wafers that are already produced (but not yet packaged).

The first respin would be from their "diffraction issue", incorrectly called a "refraction issue" by Josh in some earlier discussion:

It's kinda hard to dig up the quotes now, and it doesn't help that BFL's forums keep giving me the CloudFlare 504 error.

https://forums.butterflylabs.com/bfl-forum-miscellaneous/690-13-jan-2013-asic-update-discussion-thread-9.html#post10463

https://forums.butterflylabs.com/announcements/251-more-jalapeno-pictures-shipping-update-17-print.html (second post quotes Josh's statement.)

The second being where they claimed to be "adding clock buffers", and at the same time they changed package types:

https://bitcointalk.org/index.php?topic=128019.msg1363605#msg1363605

Ok, the first link to BFL-engineer's post is clearly pre tape out. The same with the refraction issue, thats something that would have shown up during the tapeout process. The last link doesnt contain any relevant info from BFL, just someone inferring a respin and BFL not responding to that, just to the "who pays for this" non issue. Josh just didnt want to go on record saying they hadnt succesfully taped out yet.

Its clear to me that BFL's full custom design didnt pass validations tests by the fab, and they were sent back to redo their homework. Thats a fuckup allright, and could be a big part of the delay in 2012, but its not a respin and couldnt have taken place after they (allegedly?) received first silicon.

To be clear, respin is a fairly specific term. It means you produced masks and wafers, and then have to change the mask (probably throw away the wafers). Failing a tape out process is not a respin.

[Puppet]

They also did another respin once they had working chips, I'm not sure where they switched but revision A chips couldn't use engine 0 and revision B can. Their stock firmware would actually underclock some of the revB units because they would run at >70GH/s but would overheat badly.

That sounds entirely plausible to me, and frankly, not unexpected. That would have been a respin, but it would have happened after they started shipping and wouldnt have affected their schedule. You can still produce, dice and slice the rev A chips and mount and ship them while the revised mask for rev B is taping out.