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Author Topic: Ultra Under-overclock image for A2 Innosilicon by Emdje - V5.0  (Read 79748 times)
LordTheron
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January 03, 2015, 03:21:56 AM
 #201

Apparently minereu has firmware that works with it:

The MinerEU firmware has been updated and is also reporting how many cores and temperature of the cores now. please update

new miners will still have 6 module but each pcb panel will have 12 chips instead of 8 chips. which offer a total hash rate of 120M

Maybe you can send a pm to them. I search for a link to firmware for the 110MH terminator but could not find it.

Thank you but my miners are 5 blades not 6 so I don't think they are the same. The one I have are LTC LIMITED--T SERIES.
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hdmediaservices
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January 03, 2015, 04:32:50 AM
 #202


Ok - so what is recommended for my A2 Terminator 88Mh/s units? 

I currently have the "InnoSilicon webGUI" software installed on them - which runs well and allows me to over clock to 1280 (or at least that is as far as I've gone) -- although I typically just keep them at 1200mhz.

Is there an image I can just copy onto the the builtin controller (I guess it is a Raspberry Pi) and it boots up with the new software / interface?  Something that doesn't really need any special configuration. 

I'd rather stay away from too many command lines -- as I don't want to make a typo and then they are unbootable.

Thanks for any direction on this -- or if it is even worth it?

Appreciate it!

emdje (OP)
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January 03, 2015, 11:46:12 AM
 #203

Apparently minereu has firmware that works with it:

The MinerEU firmware has been updated and is also reporting how many cores and temperature of the cores now. please update

new miners will still have 6 module but each pcb panel will have 12 chips instead of 8 chips. which offer a total hash rate of 120M

Maybe you can send a pm to them. I search for a link to firmware for the 110MH terminator but could not find it.

Thank you but my miners are 5 blades not 6 so I don't think they are the same. The one I have are LTC LIMITED--T SERIES.

I don't know that version, and I unfortunately have no suggestions on which version you could use. You could try the one for the NEW Mini terminator, but it is not stable (but coded for more chips per board). If that does not work you can try the newest version 3.0. But no guarantees it will work (it will NOT damage the miners though).
emdje (OP)
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January 03, 2015, 11:47:53 AM
 #204

Ok - so what is recommended for my A2 Terminator 88Mh/s units? 

I currently have the "InnoSilicon webGUI" software installed on them - which runs well and allows me to over clock to 1280 (or at least that is as far as I've gone) -- although I typically just keep them at 1200mhz.

Is there an image I can just copy onto the the builtin controller (I guess it is a Raspberry Pi) and it boots up with the new software / interface?  Something that doesn't really need any special configuration. 

I'd rather stay away from too many command lines -- as I don't want to make a typo and then they are unbootable.

Thanks for any direction on this -- or if it is even worth it?

Appreciate it!

If you want more overclock options (like values between 1200 and 1280, and above 1280) then you should go for version 3.0. This has extranonce support as well, providing more stable hashing at for example nicehash. You don't need to use command line stuff, just the webinterface will do.
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January 09, 2015, 12:04:44 PM
 #205

Emdje, any chance of an underclockers version?
I've undervolted my A2 and a few blades are already at 1000MHz but elec costs are now approaching revenue. I need lower frequency to get the voltage lower to extend its life a bit more. If you could add 50MHz or even 100MHz steps down to 700 or 800, that would be awesome
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January 09, 2015, 05:26:16 PM
 #206

Emdje, any chance of an underclockers version?
I've undervolted my A2 and a few blades are already at 1000MHz but elec costs are now approaching revenue. I need lower frequency to get the voltage lower to extend its life a bit more. If you could add 50MHz or even 100MHz steps down to 700 or 800, that would be awesome

Mind sharing how you were able to lower voltage on the blades?
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January 10, 2015, 10:25:54 PM
 #207

Emdje, any chance of an underclockers version?
I've undervolted my A2 and a few blades are already at 1000MHz but elec costs are now approaching revenue. I need lower frequency to get the voltage lower to extend its life a bit more. If you could add 50MHz or even 100MHz steps down to 700 or 800, that would be awesome

Mind sharing how you were able to lower voltage on the blades?

Lowering the frequency does nothing to the voltage (does lower the strain on the chips, thus lowering the current), so I assume he soldered some resistors with lower values next to the voltage regulators.

But to answer the first question. I will look at adding some more option on the lower end in the coming days. Will test it out and when it works I'll put it up.
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January 10, 2015, 11:07:43 PM
 #208

Allready tried some  Grin , but unfortunately it doesn't take yet, it switches to 1000 MHz Embarrassed
Code:
 [2015-01-11 07:04:17] Started cgminer 3.9.0                    
 [2015-01-11 07:04:17] Run Reset=1                   
 [2015-01-11 07:04:17] ST MCU hardware reset start                   
 [2015-01-11 07:04:21] SPI Speed 4000 kHz                   
 [2015-01-11 07:04:21] ST MCU - Enable (Pre-header)                   
 [2015-01-11 07:04:21] A1 = 700,40                   
 [2015-01-11 07:04:21] A1 PLL Clock = 1000MHz                   
 [2015-01-11 07:04:21] A1 = 600,40                   
 [2015-01-11 07:04:21] A1 PLL Clock = 1000MHz                   
 [2015-01-11 07:04:21] A1 = 1300,25                   
 [2015-01-11 07:04:21] A1 PLL Clock = 1300MHz                   
 [2015-01-11 07:04:21] A1 = 1300,25                   
 [2015-01-11 07:04:21] A1 PLL Clock = 1300MHz                   
 [2015-01-11 07:04:21] A1 = 1300,25                   
 [2015-01-11 07:04:21] A1 PLL Clock = 1300MHz                   
 [2015-01-11 07:04:21] A1 = 1300,25                   
 [2015-01-11 07:04:21] A1 PLL Clock = 1300MHz 

For people who are interested in overclocking, I am making progress with 4 MHz steps:
 
Code:
[2015-01-11 07:06:32] Started cgminer 3.9.0                    
 [2015-01-11 07:06:32] Run Reset=1                   
 [2015-01-11 07:06:32] ST MCU hardware reset start                   
 [2015-01-11 07:06:36] SPI Speed 4000 kHz                   
 [2015-01-11 07:06:36] ST MCU - Enable (Pre-header)                   
 [2015-01-11 07:06:36] A1 = 1304,24                   
 [2015-01-11 07:06:36] A1 PLL Clock = 1304MHz                   
 [2015-01-11 07:06:36] A1 = 1296,26                   
 [2015-01-11 07:06:36] A1 PLL Clock = 1296MHz                   
 [2015-01-11 07:06:36] A1 = 1332,17                   
 [2015-01-11 07:06:36] A1 PLL Clock = 1332MHz                   
 [2015-01-11 07:06:36] A1 = 1264,34                   
 [2015-01-11 07:06:36] A1 PLL Clock = 1264MHz                   
 [2015-01-11 07:06:36] A1 = 1272,32                   
 [2015-01-11 07:06:36] A1 PLL Clock = 1272MHz                   
 [2015-01-11 07:06:36] A1 = 1324,19                   
 [2015-01-11 07:06:36] A1 PLL Clock = 1324MHz   
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January 11, 2015, 05:28:20 PM
 #209

Hi emdje, is possible to run 2 session of cgminer in two detached console one for blade using the ssh connection?

Thanks in advance W_M

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January 11, 2015, 07:33:38 PM
 #210

Hi emdje, is possible to run 2 session of cgminer in two detached console one for blade using the ssh connection?

Thanks in advance W_M

No it is not, the pi is connected to the control board which in turn is connected to the blades. As far as I know you can only control the control board.
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January 20, 2015, 02:12:28 PM
 #211

The miner accepts the lower clock values, but somehow whatever options I add I end up with half mining speed on the pool.



Anyone any idea?

Code:
 [2015-01-20 21:49:02] Started cgminer 3.9.0                    
 [2015-01-20 21:49:02] Run Reset=1                   
 [2015-01-20 21:49:02] ST MCU hardware reset start                   
 [2015-01-20 21:49:06] SPI Speed 4000 kHz                   
 [2015-01-20 21:49:06] ST MCU - Enable (Pre-header)                   
 [2015-01-20 21:49:06] A1 = 1300,25                   
 [2015-01-20 21:49:06] A1 PLL Clock = 1300MHz                   
 [2015-01-20 21:49:06] A1 = 1300,25                   
 [2015-01-20 21:49:06] A1 PLL Clock = 1300MHz                   
 [2015-01-20 21:49:06] A1 = 1000,40                   
 [2015-01-20 21:49:06] A1 PLL Clock = 1000MHz                   
 [2015-01-20 21:49:06] A1 = 1000,40                   
 [2015-01-20 21:49:06] A1 PLL Clock = 1000MHz                   
 [2015-01-20 21:49:06] A1 = 1000,40                   
 [2015-01-20 21:49:06] A1 PLL Clock = 1000MHz                   
 [2015-01-20 21:49:06] A1 = 1000,40                   
 [2015-01-20 21:49:06] A1 PLL Clock = 1000MHz                   
 [2015-01-20 21:49:06] AUTO GPIO CS                   
 [2015-01-20 21:49:07] spidev0.0(cs0): Found 8 A1 chips                   
 [2015-01-20 21:49:07] Found chip 1 with 54 active cores                   
 [2015-01-20 21:49:07] Found chip 2 with 54 active cores                   
 [2015-01-20 21:49:07] Found chip 3 with 54 active cores                   
 [2015-01-20 21:49:07] Found chip 4 with 54 active cores                   
 [2015-01-20 21:49:07] Found chip 5 with 54 active cores                   
 [2015-01-20 21:49:07] Found chip 6 with 54 active cores                   
 [2015-01-20 21:49:07] Found chip 7 with 54 active cores                   
 [2015-01-20 21:49:07] Found chip 8 with 54 active cores                   
 [2015-01-20 21:49:07] Found 8 chips with total 432 active cores                   
 [2015-01-20 21:49:08] spidev0.0(cs1): Found 8 A1 chips                   
 [2015-01-20 21:49:08] Found chip 1 with 54 active cores                   
 [2015-01-20 21:49:08] Found chip 2 with 54 active cores                   
 [2015-01-20 21:49:08] Found chip 3 with 54 active cores                   
 [2015-01-20 21:49:08] Found chip 4 with 54 active cores                   
 [2015-01-20 21:49:08] Found chip 5 with 54 active cores                   
 [2015-01-20 21:49:08] Found chip 6 with 54 active cores                   
 [2015-01-20 21:49:08] Found chip 7 with 54 active cores                   
 [2015-01-20 21:49:08] Found chip 8 with 54 active cores                   
 [2015-01-20 21:49:08] Found 8 chips with total 432 active cores                   
 [2015-01-20 21:49:08] SPI(cs2) no device                   
 [2015-01-20 21:49:08] ACK(cs2) timeout:cmd_RESET_BCAST-0.0326s                   
 [2015-01-20 21:49:08] SPI(cs3) no device                   
 [2015-01-20 21:49:08] ACK(cs3) timeout:cmd_RESET_BCAST-0.0315s                   
 [2015-01-20 21:49:08] SPI(cs4) no device                   
 [2015-01-20 21:49:08] ACK(cs4) timeout:cmd_RESET_BCAST-0.0321s                   
 [2015-01-20 21:49:08] SPI(cs5) no device                   
 [2015-01-20 21:49:08] ACK(cs5) timeout:cmd_RESET_BCAST-0.0317s                   
 [2015-01-20 21:49:08] A1 boards=2, active cores=864, Efficient=100%, speed=32.2M                   
 [2015-01-20 21:49:08] Probing for an alive pool                   
 [2015-01-20 21:49:08] Failed to resolve (?wrong URL) /:80                   
 [2015-01-20 21:49:08] Pool 2 slow/down or URL or credentials invalid                   
 [2015-01-20 21:49:08] Pool 1 difficulty changed to 1024                                       
 [2015-01-20 21:49:08] Switching to pool 1 stratum+tcp://eu.clevermining.com:3333 - first alive pool                   
 [2015-01-20 21:49:08] Pool 0 stratum+tcp://eu-01.miningrigrentals.com:3333 alive, testing stability                   
 [2015-01-20 21:49:08] Switching to pool 0 stratum+tcp://eu-01.miningrigrentals.com:3333                   
 [2015-01-20 21:49:08] Reconnect requested from pool 0 to eu-01.miningrigrentals.com:50445                   
 [2015-01-20 21:49:09] Pool 0 difficulty changed to 128                                       
 [2015-01-20 21:49:09] Network diff set to 1.95K                                                             
 [2015-01-20 21:49:14] Network diff set to 40.4K                                                             
 [2015-01-20 21:49:14] API running in UNRESTRICTED read access mode on port 4028 (9)                   
 [2015-01-20 21:49:14] New block detected on network before longpoll                                       
(5s):12.33K (avg):31.57Kh/s (pool):0.000h/s | A:0  R:0  HW:0  WU:0.0/m
 [2015-01-20 21:49:14] chip(cs0) 5: invalid nonce 0xd1a60d00                                                     
 [2015-01-20 21:49:15] Pool 0 difficulty changed to 4096                                       
 [2015-01-20 21:49:15] Rejected 019c6469 Diff 158/128 BA1 1 pool 0 (Job '9d35' not found)                     
(5s):11.98M (avg):15.37Mh/s (pool):815.4Kh/s | A:0  R:128  HW:1  WU:746.5/m
(5s):19.94M (avg):21.03Mh/s (pool):542.0Kh/s | A:0  R:128  HW:1  WU:496.2/m
(5s):24.77M (avg):23.85Mh/s (pool):405.7Kh/s | A:0  R:128  HW:1  WU:371.5/m
(5s):27.68M (avg):25.50Mh/s (pool):326.4Kh/s | A:0  R:128  HW:1  WU:298.9/m
(5s):29.47M (avg):26.63Mh/s (pool):271.8Kh/s | A:0  R:128  HW:1  WU:248.8/m
(5s):30.56M (avg):27.44Mh/s (pool):232.7Kh/s | A:0  R:128  HW:1  WU:213.0/m
(5s):31.23M (avg):28.05Mh/s (pool):203.3Kh/s | A:0  R:128  HW:1  WU:186.2/m
(5s):31.75M (avg):28.54Mh/s (pool):180.9Kh/s | A:0  R:128  HW:1  WU:165.6/m
(5s):31.95M (avg):28.91Mh/s (pool):162.9Kh/s | A:0  R:128  HW:1  WU:149.1/m
 [2015-01-20 21:50:03] Pool 0 stale share detected, submitting and restart threads                   
 [2015-01-20 21:50:03] Pool 0 difficulty changed to 2048                                       
 [2015-01-20 21:50:03] Accepted 0173d611 Diff 45.1K/4096 BA1 0 pool 0                                       
(5s):31.70M (avg):29.13Mh/s (pool):4.895Mh/s | A:4096  R:128  HW:1  WU:4481.8/m
 [2015-01-20 21:50:06] Accepted 1f7a6272 Diff 2.08K/2048 BA1 1 pool 0                                       
(5s):31.92M (avg):29.39Mh/s (pool):6.666Mh/s | A:6144  R:128  HW:1  WU:6103.6/m
(5s):32.05M (avg):29.61Mh/s (pool):6.157Mh/s | A:6144  R:128  HW:1  WU:5636.9/m
 [2015-01-20 21:50:17] Accepted 0247bc2d Diff 28.7K/2048 BA1 0 pool 0                                       
 [2015-01-20 21:50:20] Accepted 051aa8b9 Diff 12.8K/2048 BA1 0 pool 0                                       
(5s):32.17M (avg):29.80Mh/s (pool):9.460Mh/s | A:10240  R:128  HW:1  WU:8661.3/m
 [2015-01-20 21:50:21] Accepted d6c5ba37 Diff 78.1K/2048 BA1 1 pool 0                                       
(5s):32.16M (avg):29.95Mh/s (pool):10.59Mh/s | A:12288  R:128  HW:1  WU:9693.2/m
 [2015-01-20 21:50:29] Accepted 017ca6ba Diff 44.1K/2048 BA1 1 pool 0                                       
(5s):32.20M (avg):30.10Mh/s (pool):11.57Mh/s | A:14336  R:128  HW:1  WU:10593.7/m
 [2015-01-20 21:50:33] Pool 0 difficulty changed to 4096                                       
 [2015-01-20 21:50:33] Accepted 0d9000bf Diff 4.83K/2048 BA1 0 pool 0                                       
(5s):31.95M (avg):30.18Mh/s (pool):12.44Mh/s | A:16384  R:128  HW:1  WU:11390.1/m
 [2015-01-20 21:50:37] Accepted 04bc0342 Diff 13.8K/4096 BA1 1 pool 0                                       
(5s):32.09M (avg):30.30Mh/s (pool):14.68Mh/s | A:20480  R:128  HW:1  WU:13436.4/m
 [2015-01-20 21:50:44] Accepted 043b1a13 Diff 15.5K/4096 BA1 0 pool 0                                       
(5s):32.13M (avg):30.40Mh/s (pool):16.67Mh/s | A:24576  R:128  HW:1  WU:15264.4/m
 [2015-01-20 21:50:49] Accepted 0458fb98 Diff 15.1K/4096 BA1 0 pool 0                                       
(5s):31.94M (avg):30.46Mh/s (pool):18.47Mh/s | A:28672  R:128  HW:1  WU:16906.9/m
(5s):32.30M (avg):30.57Mh/s (pool):17.59Mh/s | A:28672  R:128  HW:1  WU:16101.1/m
(5s):32.26M (avg):30.65Mh/s (pool):16.78Mh/s | A:28672  R:128  HW:1  WU:15367.1/m
 [2015-01-20 21:51:03] chip(cs1) 1: invalid nonce 0xa53abe06                                                     
(5s):32.25M (avg):30.72Mh/s (pool):16.05Mh/s | A:28672  R:128  HW:2  WU:14697.5/m
(5s):32.28M (avg):30.78Mh/s (pool):15.39Mh/s | A:28672  R:128  HW:2  WU:14091.2/m
 [2015-01-20 21:51:14] chip(cs1) 6: invalid nonce 0x351ee804                                                     
(5s):32.27M (avg):30.84Mh/s (pool):14.78Mh/s | A:28672  R:128  HW:3  WU:13533.1/m
 [2015-01-20 21:51:19] Accepted 0aa47874 Diff 6.16K/4096 BA1 0 pool 0                                       
(5s):32.27M (avg):30.90Mh/s (pool):16.25Mh/s | A:32768  R:128  HW:3  WU:14873.1/m
(5s):32.27M (avg):30.95Mh/s (pool):15.64Mh/s | A:32768  R:128  HW:3  WU:14323.3/m
(5s):32.26M (avg):30.99Mh/s (pool):15.09Mh/s | A:32768  R:128  HW:3  WU:13815.1/m
(5s):32.26M (avg):31.04Mh/s (pool):14.57Mh/s | A:32768  R:128  HW:3  WU:13343.9/m
(5s):32.26M (avg):31.08Mh/s (pool):14.10Mh/s | A:32768  R:128  HW:3  WU:12904.4/m
(5s):32.26M (avg):31.11Mh/s (pool):13.64Mh/s | A:32768  R:128  HW:3  WU:12487.9/m
 [2015-01-20 21:51:51] Pool 0 difficulty changed to 2048                                       
 [2015-01-20 21:51:51] Accepted 0fa691dc Diff 4.19K/4096 BA1 0 pool 0                                       
(5s):31.98M (avg):31.13Mh/s (pool):14.87Mh/s | A:36864  R:128  HW:3  WU:13610.4/m
 [2015-01-20 21:51:54] Accepted 134d51a3 Diff 3.4K/2048 BA1 1 pool 0                                       
(5s):32.12M (avg):31.16Mh/s (pool):15.22Mh/s | A:38912  R:128  HW:3  WU:13936.4/m
(5s):32.14M (avg):31.19Mh/s (pool):14.78Mh/s | A:38912  R:128  HW:3  WU:13532.3/m
 [2015-01-20 21:52:06] Accepted 8fde7efc Diff 117K/2048 BA1 0 pool 0                                       
 [2015-01-20 21:52:06] Accepted 1657edb2 Diff 2.93K/2048 BA1 0 pool 0                                       
(5s):32.14M (avg):31.22Mh/s (pool):15.86Mh/s | A:43008  R:128  HW:3  WU:14520.3/m
 [2015-01-20 21:52:11] Accepted 0c9021db Diff 1.33M/2048 BA1 1 pool 0                                       
(5s):32.16M (avg):31.25Mh/s (pool):16.15Mh/s | A:45056  R:128  HW:3  WU:14783.2/m
(5s):32.19M (avg):31.27Mh/s (pool):15.71Mh/s | A:45056  R:128  HW:3  WU:14381.3/m
 [2015-01-20 21:52:19] Accepted 1b1021bb Diff 2.42K/2048 BA1 0 pool 0                                       
(5s):32.19M (avg):31.30Mh/s (pool):15.98Mh/s | A:47104  R:128  HW:3  WU:14634.9/m
 [2015-01-20 21:52:23] Pool 0 difficulty changed to 4096                                       
 [2015-01-20 21:52:23] Accepted 07a9af81 Diff 8.55K/2048 BA1 0 pool 0                                       
(5s):31.92M (avg):31.30Mh/s (pool):16.24Mh/s | A:49152  R:128  HW:3  WU:14869.4/m
(5s):32.05M (avg):31.33Mh/s (pool):15.83Mh/s | A:49152  R:128  HW:3  WU:14493.8/m
(5s):32.16M (avg):31.35Mh/s (pool):15.45Mh/s | A:49152  R:128  HW:3  WU:14145.6/m
(5s):32.17M (avg):31.37Mh/s (pool):15.08Mh/s | A:49152  R:128  HW:3  WU:13805.4/m
(5s):32.20M (avg):31.39Mh/s (pool):14.72Mh/s | A:49152  R:128  HW:3  WU:13477.0/m
(5s):32.23M (avg):31.41Mh/s (pool):14.38Mh/s | A:49152  R:128  HW:3  WU:13165.3/m
(5s):32.20M (avg):31.43Mh/s (pool):14.06Mh/s | A:49152  R:128  HW:3  WU:12873.9/m
 [2015-01-20 21:53:03] chip(cs0) 2: invalid nonce 0xe92dd904                                                     
(5s):32.20M (avg):31.45Mh/s (pool):13.75Mh/s | A:49152  R:128  HW:4  WU:12587.1/m
(5s):32.51M (avg):31.48Mh/s (pool):13.46Mh/s | A:49152  R:128  HW:4  WU:12324.0/m
(5s):32.24M (avg):31.49Mh/s (pool):13.18Mh/s | A:49152  R:128  HW:4  WU:12065.2/m
(5s):32.25M (avg):31.50Mh/s (pool):12.91Mh/s | A:49152  R:128  HW:4  WU:11823.2/m
 [2015-01-20 21:53:20] Pool 0 difficulty changed to 2048                                       
 [2015-01-20 21:53:20] Accepted 0a51abb7 Diff 6.35K/4096 BA1 1 pool 0                                       
(5s):32.00M (avg):31.50Mh/s (pool):13.71Mh/s | A:53248  R:128  HW:4  WU:12549.0/m
(5s):31.89M (avg):31.51Mh/s (pool):13.44Mh/s | A:53248  R:128  HW:4  WU:12300.7/m
(5s):32.18M (avg):31.53Mh/s (pool):13.17Mh/s | A:53248  R:128  HW:4  WU:12061.5/m
 [2015-01-20 21:53:38] Accepted 15134570 Diff 3.11K/2048 BA1 0 pool 0                                       
(5s):32.23M (avg):31.55Mh/s (pool):13.42Mh/s | A:55296  R:128  HW:4  WU:12289.3/m
 [2015-01-20 21:53:42] Accepted 0279d498 Diff 26.5K/2048 BA1 0 pool 0                                       
(5s):32.27M (avg):31.56Mh/s (pool):13.66Mh/s | A:57344  R:128  HW:4  WU:12506.5/m
 [2015-01-20 21:53:45] Accepted 0c5fa1df Diff 5.3K/2048 BA1 0 pool 0                                       
(5s):32.26M (avg):31.57Mh/s (pool):13.89Mh/s | A:59392  R:128  HW:4  WU:12716.3/m
 [2015-01-20 21:53:50] chip(cs0) 5: invalid nonce 0x75a29103                                                     
(5s):32.25M (avg):31.58Mh/s (pool):13.64Mh/s | A:59392  R:128  HW:5  WU:12488.5/m
 [2015-01-20 21:53:58] Accepted 19fd503c Diff 2.52K/2048 BA1 1 pool 0                                       
(5s):32.24M (avg):31.60Mh/s (pool):13.86Mh/s | A:61440  R:128  HW:5  WU:12690.1/m
 [2015-01-20 21:54:03] Accepted 0a85b054 Diff 6.23K/2048 BA1 1 pool 0                                       
 [2015-01-20 21:54:04] Accepted 1387d14c Diff 3.35K/2048 BA1 1 pool 0                                       
(5s):32.17M (avg):31.60Mh/s (pool):14.53Mh/s | A:65536  R:128  HW:5  WU:13303.0/m
 [2015-01-20 21:54:07] Accepted 13656759 Diff 3.38K/2048 BA1 1 pool 0                                       
(5s):32.28M (avg):31.62Mh/s (pool):14.73Mh/s | A:67584  R:128  HW:5  WU:13488.8/m
(5s):32.28M (avg):31.63Mh/s (pool):14.49Mh/s | A:67584  R:128  HW:5  WU:13263.3/m
 [2015-01-20 21:54:18] Accepted 10eba7cc Diff 3.87K/2048 BA1 0 pool 0                                       
(5s):32.27M (avg):31.64Mh/s (pool):14.68Mh/s | A:69632  R:128  HW:5  WU:13439.3/m
(5s):32.44M (avg):31.66Mh/s (pool):14.45Mh/s | A:69632  R:128  HW:5  WU:13225.5/m
 [2015-01-20 21:54:26] Accepted 1a59c758 Diff 2.49K/2048 BA1 0 pool 0                                       
(5s):32.32M (avg):31.66Mh/s (pool):14.63Mh/s | A:71680  R:128  HW:5  WU:13398.0/m
 [2015-01-20 21:54:35] Accepted 0b5173f7 Diff 5.79K/2048 BA1 1 pool 0                                       
(5s):32.27M (avg):31.67Mh/s (pool):14.82Mh/s | A:73728  R:128  HW:5  WU:13568.4/m
(5s):32.29M (avg):31.68Mh/s (pool):14.60Mh/s | A:73728  R:128  HW:5  WU:13363.3/m
 [2015-01-20 21:54:44] Accepted 0aa30ef3 Diff 6.16K/2048 BA1 0 pool 0                                       
(5s):32.24M (avg):31.69Mh/s (pool):14.78Mh/s | A:75776  R:128  HW:5  WU:13528.5/m
(5s):32.23M (avg):31.70Mh/s (pool):14.55Mh/s | A:75776  R:128  HW:5  WU:13325.3/m
 [2015-01-20 21:54:52] Pool 0 stale share detected, submitting and restart threads                   
 [2015-01-20 21:54:52] Accepted 18deff78 Diff 2.63K/2048 BA1 0 pool 0                                       
 [2015-01-20 21:54:55] Accepted 1eb36ca9 Diff 2.13K/2048 BA1 0 pool 0                                       
(5s):31.95M (avg):31.69Mh/s (pool):15.11Mh/s | A:79872  R:128  HW:5  WU:13836.0/m
 [2015-01-20 21:54:59] Accepted 0306b4fa Diff 21.7K/2048 BA1 1 pool 0                                       
(5s):32.07M (avg):31.70Mh/s (pool):15.27Mh/s | A:81920  R:128  HW:5  WU:13983.9/m
 [2015-01-20 21:55:01] Accepted 18d93ec4 Diff 2.64K/2048 BA1 1 pool 0                                       
(5s):32.16M (avg):31.71Mh/s (pool):15.43Mh/s | A:83968  R:128  HW:5  WU:14127.7/m
(5s):32.18M (avg):31.72Mh/s (pool):15.21Mh/s | A:83968  R:128  HW:5  WU:13927.4/m
 [2015-01-20 21:55:12] Pool 0 difficulty changed to 4096                                       
 [2015-01-20 21:55:12] Accepted 18f8fa05 Diff 2.62K/2048 BA1 1 pool 0                                       
 [2015-01-20 21:55:14] Accepted 03f6a6a3 Diff 16.5K/4096 BA1 1 pool 0                                       
(5s):31.96M (avg):31.72Mh/s (pool):16.09Mh/s | A:90112  R:128  HW:5  WU:14736.0/m
(5s):32.02M (avg):31.72Mh/s (pool):15.87Mh/s | A:90112  R:128  HW:5  WU:14531.0/m
(5s):32.24M (avg):31.73Mh/s (pool):15.66Mh/s | A:90112  R:128  HW:5  WU:14337.0/m
(5s):32.24M (avg):31.74Mh/s (pool):15.45Mh/s | A:90112  R:128  HW:5  WU:14149.1/m
(5s):32.25M (avg):31.75Mh/s (pool):15.25Mh/s | A:90112  R:128  HW:5  WU:13964.3/m
 [2015-01-20 21:55:36] Accepted 0464fe60 Diff 14.9K/4096 BA1 0 pool 0                                       
(5s):32.24M (avg):31.75Mh/s (pool):15.74Mh/s | A:94208  R:128  HW:5  WU:14408.4/m
(5s):32.26M (avg):31.76Mh/s (pool):15.54Mh/s | A:94208  R:128  HW:5  WU:14225.8/m
(5s):32.26M (avg):31.77Mh/s (pool):15.34Mh/s | A:94208  R:128  HW:5  WU:14046.5/m
 [2015-01-20 21:55:54] chip(cs0) 7: invalid nonce 0x4f0cd70c                                                     
 [2015-01-20 21:55:56] chip(cs0) 8: invalid nonce 0x09416613                                                     
(5s):32.28M (avg):31.77Mh/s (pool):15.15Mh/s | A:94208  R:128  HW:7  WU:13872.8/m
 [2015-01-20 21:56:02] Shutdown signal received.                   
 [2015-01-20 21:56:02]
Summary of runtime statistics:
                   
 [2015-01-20 21:56:02] Started at [2015-01-20 21:49:09]                   
 [2015-01-20 21:56:02] Runtime: 0 hrs : 6 mins : 53 secs                   
 [2015-01-20 21:56:02] Average hashrate: 32.1 Megahash/s                   
 [2015-01-20 21:56:02] Solved blocks: 0                   
 [2015-01-20 21:56:02] Best share difficulty: 1.33M                   
 [2015-01-20 21:56:02] Share submissions: 38                   
 [2015-01-20 21:56:02] Accepted shares: 37                   
 [2015-01-20 21:56:02] Rejected shares: 1                   
 [2015-01-20 21:56:02] Accepted difficulty shares: 94208                   
 [2015-01-20 21:56:02] Rejected difficulty shares: 128                   
 [2015-01-20 21:56:02] Reject ratio: 2.6%                   
 [2015-01-20 21:56:02] Hardware errors: 7                   
 [2015-01-20 21:56:02] Utility (accepted shares / min): 5.44/min                   
 [2015-01-20 21:56:02] Work Utility (diff1 shares solved / min): 13872.84/min
                   
 [2015-01-20 21:56:02] Stale submissions discarded due to new blocks: 0                   
 [2015-01-20 21:56:02] Unable to get work from server occasions: 0                   
 [2015-01-20 21:56:02] Work items generated locally: 362                   
 [2015-01-20 21:56:02] Submitting work remotely delay occasions: 0                   
 [2015-01-20 21:56:02] New blocks detected on network: 2
                   
 [2015-01-20 21:56:02] Pool: stratum+tcp://eu-01.miningrigrentals.com:3333                   
 [2015-01-20 21:56:02]  Share submissions: 38                   
 [2015-01-20 21:56:02]  Accepted shares: 37                   
 [2015-01-20 21:56:02]  Rejected shares: 1                   
 [2015-01-20 21:56:02]  Accepted difficulty shares: 94208                   
 [2015-01-20 21:56:02]  Rejected difficulty shares: 128                   
 [2015-01-20 21:56:02]  Reject ratio: 2.6%                   
 [2015-01-20 21:56:02]  Items worked on: 331                   
 [2015-01-20 21:56:02]  Stale submissions discarded due to new blocks: 0                   
 [2015-01-20 21:56:02]  Unable to get work from server occasions: 0                   
 [2015-01-20 21:56:02]  Submitting work remotely delay occasions: 0
                   
 [2015-01-20 21:56:02] Pool: stratum+tcp://eu.clevermining.com:3333                   
 [2015-01-20 21:56:02]  Share submissions: 0                   
 [2015-01-20 21:56:02]  Accepted shares: 0                   
 [2015-01-20 21:56:02]  Rejected shares: 0                   
 [2015-01-20 21:56:02]  Accepted difficulty shares: 0                   
 [2015-01-20 21:56:02]  Rejected difficulty shares: 0                   
 [2015-01-20 21:56:02]  Items worked on: 1                   
 [2015-01-20 21:56:02]  Stale submissions discarded due to new blocks: 0                   
 [2015-01-20 21:56:02]  Unable to get work from server occasions: 0                   
 [2015-01-20 21:56:02]  Submitting work remotely delay occasions: 0
                   
 [2015-01-20 21:56:02] Pool: http:///                   
 [2015-01-20 21:56:02]  Share submissions: 0                   
 [2015-01-20 21:56:02]  Accepted shares: 0                   
 [2015-01-20 21:56:02]  Rejected shares: 0                   
 [2015-01-20 21:56:02]  Accepted difficulty shares: 0                   
 [2015-01-20 21:56:02]  Rejected difficulty shares: 0                   
 [2015-01-20 21:56:02]  Items worked on: 0                   
 [2015-01-20 21:56:02]  Stale submissions discarded due to new blocks: 0                   
 [2015-01-20 21:56:02]  Unable to get work from server occasions: 0                   
 [2015-01-20 21:56:02]  Submitting work remotely delay occasions: 0
                   
 [2015-01-20 21:56:02] Summary of per device statistics:
                   
 [2015-01-20 21:56:02] BA10                | (5s):16.13M (avg):16.06Mh/s | A:55296 R:0 HW:5 WU:8131.7/m                   
 [2015-01-20 21:56:03] BA11                | (5s):16.13M (avg):16.06Mh/s | A:38912 R:128 HW:2 WU:5741.1/m                   
 [2015-01-20 21:56:03]                     
emdje (OP)
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February 02, 2015, 02:13:27 PM
 #212


A2 board after I took the heat sink off. You can see the four voltage regulator circuits (two in the middle of the board on the sides, and two almost on the top of the board)


Dahmn those SMD risistors are small  Tongue 
I could not find SMD resistors of the right size or quantity below 100, so I took some high precision 'normal' ones of 12.7k (measured all around 12.36k) and soldered four on one of my two boards.

Will post screen-shot to show improvement in hardware errors. Seems like there is a lot of improvement Smiley
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February 02, 2015, 02:46:47 PM
Last edit: February 02, 2015, 10:12:53 PM by emdje
 #213



Board 0, is the original one, with HW error % of: (40*100)/(369+40)=9.78%
Board 1, is the tweaked one, with HW error % of: (1*100)/(408+1)=0.24%

Update: It is now 1.5 hours later and board 1 still has only 1 HW error, board 0 now has 75.
Update 2: 8 hours later, board 1: 6 HW errors, board 0: 208 HW errors

Pretty good difference  Grin


Temperature difference is significant though.
quakefiend420
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February 03, 2015, 02:41:59 AM
 #214

So you're overvolting?  How much?  What's the difference in power consumption?  Any more frequency headroom?
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February 03, 2015, 06:17:20 AM
 #215

Awesome! More details!  Grin
emdje (OP)
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February 03, 2015, 08:53:06 AM
 #216

Yes I am overvolting.
The original resistor (05c value ~ 11k) was about .84 volt. I soldered 12.7 k (measured 12.4k), which is about .90 to .92 Volt.
I have not measured the power consumption yet.

Yes it allows me to set the chip to a higher frequency. Board 1 is hashing stable at a frequency of 1320 MHz, and after 10.5 hours shows only 10 HW errors. Board 0, which is at 1300 MHz shows 284 HW errors.
I will try higher settings later Smiley
And when I measured power consumption I'll post the reading.
quakefiend420
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February 04, 2015, 07:26:35 AM
 #217

Yes I am overvolting.
The original resistor (05c value ~ 11k) was about .84 volt. I soldered 12.7 k (measured 12.4k), which is about .90 to .92 Volt.
I have not measured the power consumption yet.

Yes it allows me to set the chip to a higher frequency. Board 1 is hashing stable at a frequency of 1320 MHz, and after 10.5 hours shows only 10 HW errors. Board 0, which is at 1300 MHz shows 284 HW errors.
I will try higher settings later Smiley
And when I measured power consumption I'll post the reading.

Interested to see what happens here...nice work!
emdje (OP)
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February 04, 2015, 07:34:28 AM
 #218

Put the overvolted board on 1400 MHz. Has been running for over 22 hours and produced only Shocked 34 HW errors.
The other board at 1300 MHz produced 591 HW errors, and if I put that board on 1400 I effectively cripple it.
wolf_miner
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February 04, 2015, 07:59:18 PM
 #219

Hi, looking at stat page I have a chip with a higher temperature, all the chips are at about 40° but one is at 62°, How can i solve the problem?

Thanks W_M
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February 04, 2015, 09:03:37 PM
Last edit: February 04, 2015, 11:34:19 PM by Prelude
 #220

Put the overvolted board on 1400 MHz. Has been running for over 22 hours and produced only Shocked 34 HW errors.
The other board at 1300 MHz produced 591 HW errors, and if I put that board on 1400 I effectively cripple it.

Wow, that's great! Might have to do the same mod, I have 1 88MH unit and 1 60MH unit. Good job!

How fast is the blade hashing at 1400mhz?
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