Block Erupter Prisma (>=1.4 T/device, 0.75-0.78 W/G, <1 BTC/T, October Shipping)

[jimmothy]

Looks like a longer tube. How did they get the efficiency up?

Downclock and downvolt each chip.

Nope. Its a new parallel powering layout which is simply more efficient. If I get a Prisma you'll be able to see it in the pictures.

That may be true but it's also underclocked. The tubes were 8.3gh/s per chip and Prisma is 7.3gh/s.

Where did you hear about this "parallel powering layout"?

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[dogie]

Looks like a longer tube. How did they get the efficiency up?

Downclock and downvolt each chip.

Nope. Its a new parallel powering layout which is simply more efficient. If I get a Prisma you'll be able to see it in the pictures.

That may be true but it's also underclocked. The tubes were 8.3gh/s per chip and Prisma is 7.3gh/s.

Where did you hear about this "parallel powering layout"?

Downclocking the chips by 10% doesn't result in 25% power savings. The design was first done by XBTec on their Pacifics (https://farm4.staticflickr.com/3874/14825302026_f8e55aca1f_o.jpg) which results in significantly lower power requirements by stringing the chips together. [Note their V1 didn't actually realise the power savings in the design due to other bottlenecks, but the V2 did]. This is the same 'technology' that friedcat has put on the Prisma to generate the power savings compared to the Tube.

[hdbuck]

Looks like a longer tube. How did they get the efficiency up?

Downclock and downvolt each chip.

Nope. Its a new parallel powering layout which is simply more efficient. If I get a Prisma you'll be able to see it in the pictures.

That may be true but it's also underclocked. The tubes were 8.3gh/s per chip and Prisma is 7.3gh/s.

Where did you hear about this "parallel powering layout"?

Downclocking the chips by 10% doesn't result in 25% power savings. The design was first done by XBTec on their Pacifics (https://farm4.staticflickr.com/3874/14825302026_f8e55aca1f_o.jpg) which results in significantly lower power requirements by stringing the chips together. [Note their V1 didn't actually realise the power savings in the design due to other bottlenecks, but the V2 did]. This is the same 'technology' that friedcat has put on the Prisma to generate the power savings compared to the Tube.

is it possible to reach 2Th by overclocking say 1 chip out of 2 (and considering the chip density) or something?

[klondike_bar]

Looks like a longer tube. How did they get the efficiency up?

Downclock and downvolt each chip.

Nope. Its a new parallel powering layout which is simply more efficient. If I get a Prisma you'll be able to see it in the pictures.

That may be true but it's also underclocked. The tubes were 8.3gh/s per chip and Prisma is 7.3gh/s.

Where did you hear about this "parallel powering layout"?

Downclocking the chips by 10% doesn't result in 25% power savings. The design was first done by XBTec on their Pacifics (https://farm4.staticflickr.com/3874/14825302026_f8e55aca1f_o.jpg) which results in significantly lower power requirements by stringing the chips together. [Note their V1 didn't actually realise the power savings in the design due to other bottlenecks, but the V2 did]. This is the same 'technology' that friedcat has put on the Prisma to generate the power savings compared to the Tube.

is that the stringing to run them off 12V without massive losses on the DC/DC converters?

[novak@gekkoscience]

Looks like a longer tube. How did they get the efficiency up?

Downclock and downvolt each chip.

Nope. Its a new parallel powering layout which is simply more efficient. If I get a Prisma you'll be able to see it in the pictures.

Interesting, Dogie.  I assume you have some inside information.  Looking at the prisma image it's pretty hard to see what's going on, almost looks intentionally blurred over the area that previously contained the buck circuits.  I think it's just a low quality image, but that particular area is pretty blurry.  It looks like maybe there are a couple of ICs in the area, potentially level shifters between the BEE200 chips and the AVR for SPI communication?  And I am pretty sure I do see caps in between each BE200 chip, which would make sense.

--
novak

[TheRealSteve]

Looking at the prisma image it's pretty hard to see what's going on [...] I think it's just a low quality image

		Pretty much.  I'm sure higher quality pictures will pop up as people get these in hand (asicminer could take some themselves, of course).
		Here's some different angles, but they're really not that much clearer

[novak@gekkoscience]

Looking at the prisma image it's pretty hard to see what's going on [...] I think it's just a low quality image

Pretty much.  I'm sure higher quality pictures will pop up as people get these in hand (asicminer could take some themselves, of course).  Here's some different angles, but they're really not that much clearer

It does look like a lot of buffer ICs (or something) from that picture and there are certainly caps, I can't really tell what's on the other side of the chips though...  I'm not certain of the exact way that these are being hooked up, but the core voltage is somewhere between 0.55 and 0.88 V, and 16 in series under 12V would be 0.75V per chip, which would be reasonable.  Maybe on the other side of the chips are low power bucks to generate the correct I/O voltage for each chip (1.8V above whatever ground level is).

Interesting, at any rate.

--
novak

[xhomerx10]

Looks like a longer tube. How did they get the efficiency up?

Downclock and downvolt each chip.

Nope. Its a new parallel powering layout which is simply more efficient. If I get a Prisma you'll be able to see it in the pictures.

That may be true but it's also underclocked. The tubes were 8.3gh/s per chip and Prisma is 7.3gh/s.

Where did you hear about this "parallel powering layout"?

Downclocking the chips by 10% doesn't result in 25% power savings. The design was first done by XBTec on their Pacifics (https://farm4.staticflickr.com/3874/14825302026_f8e55aca1f_o.jpg) which results in significantly lower power requirements by stringing the chips together. [Note their V1 didn't actually realise the power savings in the design due to other bottlenecks, but the V2 did]. This is the same 'technology' that friedcat has put on the Prisma to generate the power savings compared to the Tube.

 While I respect AM and your guides Dogie, I have to respectfully disagree -

 The math:
800(speed of the tube) X 240/270(ratio of clocks) X 2(ratio of chips per miner) = 1422
 and because you have underclocked you can now lower the voltage resulting in some power savings.
Come on man we've all done this with our GPUs; this is nothing different or special and nothing they couldn't have done right off the hop to give AM an edge.

 parallell powering layout my ASS.  Who came up with this BS?

[Cyper_BLC]

hash rate per watt not a problem, it can be solved easly with loverclock Major problem is Block Erupter's ugly user interface named: "BE200 Jet stratum miner", rockminer solve this problem with new r4 box model but Asicminer using still oldschool ugly BlockErupter thing. Thats terrible. Now i must to ask this, anyone can try http://getminera.com/ interface ? beatiful...

or maybe they can use this:
http://www.dragino.com/products/linux-module/item/87-he.html  ------ this is 15$ bitmain biggest solution.
https://github.com/dragino
like antminer s3.

i hope FriedCat answers this message.

[CanaryInTheMine]

hash rate per watt not a problem, it can be solved easly with loverclock Major problem is Block Erupter's ugly user interface named: "BE200 Jet stratum miner", rockminer solve this problem with new r4 box model but Asicminer using still oldschool ugly BlockErupter thing. Thats terrible. Now i must to ask this, anyone can try http://getminera.com/ interface ? beatiful...

or maybe they can use this:
http://www.dragino.com/products/linux-module/item/87-he.html  ------ this is 15$ bitmain biggest solution.
https://github.com/dragino
like antminer s3.

i hope FriedCat answers this message.

You're idiotically clueless...

[Tigggger]

The price is good and the improved power consumption means that they have a much longer lifespan, but....

For me I now ship all my miners to be hosted as I save the import tax and it costs less to run than it does here due to the high UK electric rates.

So I'd really like to buy a lot of these but they aren't really suited to mass deployment as it's a lot of work and fiddling around for my data centre and they aren't easily rackable

What I need is an all in one machine similar to the S2/S4, a nice case containing a pi or similar to run the blades and an optional PSU, anyone working on something like that ?

[sepehr]

Hi Friedcat,

I need many devices, 100 or maybe more,

Can you ship two devices per shipment? and in separate names and destinations?
I need that for custom clearance.

For example if I order 40 Devices. can you ship 20 Shipments each including 2 devices to separate destinations and names?

Also the other question is can I arrange for pickup from your factory by my favorite shipment agaency?

Thanks,
Sepehr

[dogie]

 While I respect AM and your guides Dogie, I have to respectfully disagree -

 The math:
800(speed of the tube) X 240/270(ratio of clocks) X 2(ratio of chips per miner) = 1422
 and because you have underclocked you can now lower the voltage resulting in some power savings.
Come on man we've all done this with our GPUs; this is nothing different or special and nothing they couldn't have done right off the hop to give AM an edge.

 parallell powering layout my ASS.  Who came up with this BS?

The guy with inside information maybe? But your math checks out so it's k, lets go with that. I'm sure friedcat purposely made the tubes consume an additional 50% power for no reason.

[bitsalame]

8 pages already with trolling and flaming, can we just delete everything and start over?
This is supposed to be a sales page, and it is already 90% offtopic.

[xhomerx10]

 While I respect AM and your guides Dogie, I have to respectfully disagree -

 The math:
800(speed of the tube) X 240/270(ratio of clocks) X 2(ratio of chips per miner) = 1422
 and because you have underclocked you can now lower the voltage resulting in some power savings.
Come on man we've all done this with our GPUs; this is nothing different or special and nothing they couldn't have done right off the hop to give AM an edge.

 parallell powering layout my ASS.  Who came up with this BS?

The guy with inside information maybe? But your math checks out so it's k, lets go with that. I'm sure friedcat purposely made the tubes consume an additional 50% power for no reason.

 It is the chips on the tube not the tube itself consuming the power as you well know.  There are more chips on the Prisma which are underclocked and undervolted as compared to the tube.  To simply state the Tubes consume an additional 50% is an over-simplification.
Also, friedcat didn't purposely make the tubes, it was an open-sourced design with core voltage of 0.8

 AM was trying to sell as many chips as possible to maximize their profit - that's the simple and reasonable explanation.  The new design means selling more chips which is great, but I don't believe have made any significant technical advances in design.

[dogie]

 While I respect AM and your guides Dogie, I have to respectfully disagree -

 The math:
800(speed of the tube) X 240/270(ratio of clocks) X 2(ratio of chips per miner) = 1422
 and because you have underclocked you can now lower the voltage resulting in some power savings.
Come on man we've all done this with our GPUs; this is nothing different or special and nothing they couldn't have done right off the hop to give AM an edge.

 parallell powering layout my ASS.  Who came up with this BS?

The guy with inside information maybe? But your math checks out so it's k, lets go with that. I'm sure friedcat purposely made the tubes consume an additional 50% power for no reason.

 It is the chips on the tube not the tube itself consuming the power as you well know.  There are more chips on the Prisma which are underclocked and undervolted as compared to the tube.  To simply state the Tubes consume an additional 50% is an over-simplification.
Also, friedcat didn't purposely make the tubes, it was an open-sourced design with core voltage of 0.8

 AM was trying to sell as many chips as possible to maximize their profit - that's the simple and reasonable explanation.  The new design means selling more chips which is great, but I don't believe have made any significant technical advances in design.

*facepalm*

[Blazed]

So far we got 2 USA group buys going on.. Canary and CrazyGuy. Go look in "Group Buys" to find them!

[hdbuck]

So far we got 2 USA group buys going on.. Canary and CrazyGuy. Go look in "Group Buys" to find them!

CrazyGuy is no USA. He is Europe (France).

[Blazed]

So far we got 2 USA group buys going on.. Canary and CrazyGuy. Go look in "Group Buys" to find them!

CrazyGuy is no USA. He is Europe (France).

No he is USA same with Canary..

https://bitcointalk.org/index.php?topic=795477.msg8958826#msg8958826

How else would he have a USA zip code + use USPS to ship?

[hdbuck]

So far we got 2 USA group buys going on.. Canary and CrazyGuy. Go look in "Group Buys" to find them!

CrazyGuy is no USA. He is Europe (France).

No he is USA same with Canary

is he?

What's your zip code? Just to get a rough idea of shipping costs.

Is USPS the only option or can you accept FedEx/UPS labels too?

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