Block Erupter: Dedicated Mining ASIC Project (Open for Discussion)

[friedcat]

13W at 17 square mm - seems like a significant mount of heat to deal with.

When I was a kid, I used to have a 25W soldering iron and it was melting solder perfectly well.

Well, directly decreasing both the voltage and the frequency will dramatically reduce the power consumption. But the hashing rate per wafer will also reduce. This statistics is basically a result of trying to drive the hashrate/area to the highest given our 130nm choice. We will fix the whole design in the earlier iteration of back-end, then we probably will get a better compromise.

[1713522120]

1713522120

[rjk]

So about 5 times better than current LX150 chips/bitstreams in terms of hash rate per watt, is that about right? And this is on 130nm? Are you able to guess how much improvement might be had with a straight die shrink?

[piotr_n]

13W at 17 square mm - seems like a significant mount of heat to deal with.

When I was a kid, I used to have a 25W soldering iron and it was melting solder perfectly well.

Well, directly decreasing both the voltage and the frequency will dramatically reduce the power consumption. But the hashing rate per wafer will also reduce. This statistics is basically a result of trying to drive the hashrate/area to the highest given our 130nm choice. We will fix the whole design in the earlier iteration of back-end, then we probably will get a better compromise.

Yeah, I was just saying that one of your challenges will be how to drain the heat out of the tiny chips.
Especially assuming that you'd probably want to have a single PCB with many of such chips working in parallel.

[friedcat]

So about 5 times better than current LX150 chips/bitstreams in terms of hash rate per watt, is that about right? And this is on 130nm? Are you able to guess how much improvement might be had with a straight die shrink?

It's hard to give an accurate guess. But I believe that the power consumption is (way) proportional to total area if the circuit structure does not change. We haven't investigated die shrink from the foundry yet but currently anything beyond 130nm is also beyond our budget.

[friedcat]

13W at 17 square mm - seems like a significant mount of heat to deal with.

When I was a kid, I used to have a 25W soldering iron and it was melting solder perfectly well.

Well, directly decreasing both the voltage and the frequency will dramatically reduce the power consumption. But the hashing rate per wafer will also reduce. This statistics is basically a result of trying to drive the hashrate/area to the highest given our 130nm choice. We will fix the whole design in the earlier iteration of back-end, then we probably will get a better compromise.

Yeah, I was just saying that one of your challenges will be how to drain the heat out of the tiny chips.
Especially assuming that you'd probably want to have a single PCB with many of such chips working in parallel.

This kind of heat density is not very common. The hardware implementation of SHA-2 involves too many unavoidable registers, and they all flip frequently. Larger heat sinks will do the work, but they reduce the density of chips on a single PCB. Also we have clock-lowering and the voltage-lowering as the last resort.

Anyway this problem will definitely be tackled. Fortunately our first batch of chips will probably consumed by ourselves, so the requirements of PCB design will be lower than that of a full-fledged Rig design, and heat issues are more tolerable at this stage. Of course, making high-quality mining devices that's usable by retail buyers is another story, and more challenging.

[punin]

This kind of heat density is not very common. The hardware implementation of SHA-2 involves too many unavoidable registers, and they all flip frequently. Larger heat sinks will do the work, but they reduce the density of chips on a single PCB. Also we have clock-lowering and the voltage-lowering as the last resort.

Anyway this problem will definitely be tackled. Fortunately our first batch of chips will probably consumed by ourselves, so the requirements of PCB design will be lower than that of a full-fledged Rig design, and heat issues are more tolerable at this stage. Of course, making high-quality mining devices that's usable by retail buyers is another story, and more challenging.

Any specs or pinouts yet?

[2112]

Larger heat sinks will do the work, but they reduce the density of chips on a single PCB.

Don't forget to ask the analog side of your fab for the suggestions on the casing. If you use serial I/O then 8 pins should be plenty. And if you need only 8 pins you could use one of the many IC cases designed for power analog application with a screw-hole for the heatsink mounting. The PCB will be an afterthought distribution strip. The power heatsink bars are ultra cheap and sold by the linear feet.

Good luck.

[2112]

Sorry if this is a stupid question, can the chip be split up so the hot running operations run separately to the simper ones? Would guess that would let you focus on optimizing the bottleneck while the cooler functions can run on a cheaper chip.

Too many pins would be required to shuffle the data between the hot and cold parts. Essentially the whole hashing chip is hot.

What makes sense is to use a single chip with split clocks and split power supply. One clock and power for the "core" and one clock and power for the "I/O".

The split you suggesting also makes sense for the "full custom" versus "cell library" choices. Use "full custom" for the core hashing round and "cell library" for all the glue logic. But I don't think that the fab the Block Erupter uses would allow them to do this. It seems like they are committed to the cell library only design.

Edit: Here's the link to how Xilinx uses two-process' (65nm and 28nm) split for their $10k per chip Virtex-7 line.

http://www.xilinx.com/support/documentation/white_papers/wp380_Stacked_Silicon_Interconnect_Technology.pdf

[nedbert9]

Hot hot hot.

This sounds like a job for the Sandia Cooler.

[2112]

Is that multilayered layout way above normal budgets and are there cooling issues with it?

Multilayer silicon is simply not required. The Bitcoin hasher chip is extraordinarily simple as far as digital design goes. The only unusual part is the power dissipation per area-unit. Somebody experienced with power analog design should be able to solve it quickly and without much expense.

It is basically a lottery-ticket buying machine. Even if cetrain fraction of the tickets is mangled the whole machine is still worth it. There will be no yield issues: it will be either zero (completely doesn't work) or nearly 100%.

[Lethos]

Great to hear the news of this ASIC project, nice numbers too.

[jjshabadoo]

As long as your plan isn't to hold onto everyone's money for months, you'll sell a bunch of these. I'd buy a few units just to support the network and not give a crap about mining returns. I think many others would as well.

Also, if you really hope to have success selling these units, just get them ready before BFL and you're going to sell as many as you can produce.

[friedcat]

Essentially the whole hashing chip is hot.

Yes, especially that the hashing units themselves take over almost all the chip area.

What makes sense is to use a single chip with split clocks and split power supply. One clock and power for the "core" and one clock and power for the "I/O".

Yes. We made this decision from the start. The typical voltage for powering the I/O is way too high for the whole chip.

The split you suggesting also makes sense for the "full custom" versus "cell library" choices. Use "full custom" for the core hashing round and "cell library" for all the glue logic. But I don't think that the fab the Block Erupter uses would allow them to do this. It seems like they are committed to the cell library only design.

Exactly. In fact the glue logic only occupies a tiny part of each chip, all the rest parts are for hashing. And a full custom design is too impractical for us.

Edit: Here's the link to how Xilinx uses two-process' (65nm and 28nm) split for their $10k per chip Virtex-7 line.

http://www.xilinx.com/support/documentation/white_papers/wp380_Stacked_Silicon_Interconnect_Technology.pdf

Thanks again for your link.

[friedcat]

As long as your plan isn't to hold onto everyone's money for months, you'll sell a bunch of these. I'd buy a few units just to support the network and not give a crap about mining returns. I think many others would as well.

Also, if you really hope to have success selling these units, just get them ready before BFL and you're going to sell as many as you can produce.

We divide our business into two large stages. The first one is to make prototypes consumed by us. The second one is to design higher quality mining devices for selling. Or in the second stage we could find some partner to do the whole PCB/case/repairing/custom service/logistics for us. But both options need more time. So thanks very much for your expectation, but it will be later to deliver nice products for sale than deploying the first batch of chips for ourselves.

[friedcat]

Update

We decided to apply more manual optimizations to further increase the power efficiency. Since our chips will be mass produced, we believe some more time spent on making each chip better is worth it.

[punin]

As long as your plan isn't to hold onto everyone's money for months, you'll sell a bunch of these. I'd buy a few units just to support the network and not give a crap about mining returns. I think many others would as well.

Also, if you really hope to have success selling these units, just get them ready before BFL and you're going to sell as many as you can produce.

We divide our business into two large stages. The first one is to make prototypes consumed by us. The second one is to design higher quality mining devices for selling. Or in the second stage we could find some partner to do the whole PCB/case/repairing/custom service/logistics for us. But both options need more time. So thanks very much for your expectation, but it will be later to deliver nice products for sale than deploying the first batch of chips for ourselves.

You might not want to spend too much time on your own miners if your tape-out is successful. I'd do a reference PCB design, test it, and release it asap together with the chips. You'll make much more money selling the chips and maybe licensing the reference design, than by mining yourself. Time is your enemy here.

[Lethos]

13 Watts is not that bad, and if you could improve it, brilliant, but it's still in the region of some of the more powerful Intel Atom chips and they are not hard to cool down. Also with going down to 65nm (and lower) designs eventually I assume you'll be going to very low single digits which is awesome, by the nature of scaling.

Great Job !

[friedcat]

You might not want to spend too much time on your own miners if your tape-out is successful. I'd do a reference PCB design, test it, and release it asap together with the chips. You'll make much more money selling the chips and maybe licensing the reference design, than by mining yourself. Time is your enemy here.

Of course, but product quality and customers' words of mouth are the life of a company. But we don't want to sell prototypes. We want to sell mining devices with a higher standard. We ourselves could probably handle second-digit rates of failure, some heat issues, and sketchy appearances. But we wouldn't want our customers to have to deal with them.

[friedcat]

13 Watts is not that bad, and if you could improve it, brilliant, but it's still in the region of some of the more powerful Intel Atom chips and they are not hard to cool down. Also with going down to 65nm (and lower) designs eventually I assume you'll be going to very low single digits which is awesome, by the nature of scaling.

Great Job !

Thanks for your appreciation.

We are on our way of lowering the power consumption down to less than 10W while keeping the same hashrate per mm^2. And please don't rely on the data too much because the back-end stage's power estimation makes more sense.

[punin]

You might not want to spend too much time on your own miners if your tape-out is successful. I'd do a reference PCB design, test it, and release it asap together with the chips. You'll make much more money selling the chips and maybe licensing the reference design, than by mining yourself. Time is your enemy here.

Of course, but product quality and customers' words of mouth are the life of a company. But we don't want to sell prototypes. We want to sell mining devices with a higher standard. We ourselves could probably handle second-digit rates of failure, some heat issues, and sketchy appearances. But we wouldn't want our customers to have to deal with them.

This is exactly why I suggest you do a reference PCB design, and roll it out ASAP together with the chips. There's no point for you taking care of all the hassle associated with B-to-C sales like warranty, after sales etc. You customers should be mining rig manufacturers or able hobbyists, not end consumers. Sell the chip like xilinx sells spartans. License the ref design PCB or just release it open source. Scale up quick, time is your enemy.