Hello,
I want to know how much will the dev kit cost.
Thanks.

show some pics or it didn't happen

spiccioli

AES-KEY within Spartan6 protects IP no way better, EldenTyrell however pointed me on that, so my delivery idea failed.

Didn't take you long, did it?

No, seriously, this pre-announcement will pull the rug out from underneath all other vendors - the Icarus/Lancelot guy in mainland China, Stefan in Germany, the British guys, the American guys with their 6500 board, even the genius-level bitstream guys like EldenTyrell and Bitfury.

It's going to be a bloodbath.

<let's get it shorter.>

Keep in mind, you have to add 11 TH/s to get anywhere near a 51% attack, and at that point you would be mining ~3600 Bitcoin per day. If you are generating that much, it is actually in your best interest to *not* attack the network, and let someone else develop ASIC as the price increases because demand will remain the same but supply will slow down.

I know a number of people talk about what will happen when the reward halves, but what would happen if a large investor developed ASIC to control a significant stake of the Bitcoin network? Wouldn't it essentially be the same result if difficulty doubled as if the reward halved?

About 28 nm FPGAs chances... I've counted approximately translation of FPGA into ASIC. for example if my design translated - it would get approximately 8.7 million transistors count. And it is comparable to Pentium II design, so what we have with Spartan-6 0.045 um (45 nm) is what you could get if you squeeze hard into 0.35 um ASIC.

But squeezing design so hard into ASIC would be difficult, as many errors will happen on the way. It is LIKELY that builders of ASICs would squeeze more or less kind of simple VHD design, which would give approx. 3 times worse performance, and then start gradually improve technology with about 3-4 month iteration with each try. I think ngzhang understands well, what design mistakes - when in simulators it works but in hardware does not means when it gets to ASIC production.

So back to issue about ASIC vs FPGA - I suppose that 45 nm equivalent FPGA of Spartan6 class like 0.18 um ASIC.
Then 28 nm FPGA Artix7 could be like 0.112 um ASIC (if just counted, but I suppose comparable to 90 nm more, because it has CARRY CHAIN IN EVERY SLICE, AND I HAVE ROUND DESIGN THAT USES THIS FACT, AND WHICH IS 20% smaller Spartan6 is really bad with their Slice X stuff).

Then interesting thing about FPGA prices. They will fall if volumes will be bulk. This is why I am insisting on making FPGA-based products better, with better pricing - to make it at least competitive against ASICs.

Also - costs for chip production for vendor like Xilinx or Altera is not that much than silicon costs.... So production Spartan6 or Virtex7 does not make much difference in raw material / work cost. If they would want - they could sell say 6.8 billion transistor chip for $60-70 and not for $1k-$2k for specific needs, still they would earn profits. And this is huge risk for ASIC builders. Such chip indeed would be very powerful and definitely would blow off low-end 90 nm ASIC solution. And this is what could happen - Xil or Altera will just lower prices for some specific application of their chip, to take share of this. But this will only happen of course if there will be more or less significant sales amount, say we get all-together to levels 10k chips per month.

So there's no "cheap and secure" entry into ASIC world. Those who go with 90 nm will still compete with FPGA. And it is just only about organization of FPGA sales and production, if FPGA devices vendors would have so high expenses, that they could not resist such ASIC.

The killing solution however would be to get 28-nm chip with SIMPLE design from first order. It is doable, I believe in about $4 - $6 mio. But I doubt that someone would invest it this day. At some day it will happen of course. I quoted multiple companies already about ASIC when did FPGA-based design, and typically 90nm with investments about $500k could blow off Spartans, but would be hard to compete against 28-nm.

So, please comment ? If this is just hobby for you and you won't like to stand head-to-head with upcoming ASIC or not ?

Why do you think that 28-nm would not compete ?

You probably have up to date worked the most on bitstream design as well. Interested to hear your point of view, where I made mistake ?

Haha, yes I know they will, but if the 28nms come out before the ASICs they will at least have a chance of entering the market

So the real contest is time; 28nm vs ASICs.

Sounds good!

I'm looking forward to seeing how Lancelot will compete with all of the newer FPGAs and possibly ASICs being thrown into the market.

Elaborate please.

any updates?

My guess is xiangfu is selling his Icarus to make room for the Lancelots he'll be testing for ngzhang.

My point was, that 8 x 32 is not 240. It is 256.
If you can fit this in only 240 slices, then maybe 16 x 15 is a better geometry, since 16 x 15 really is 240.
Or am I missing the point here?

Could it be related to the fact that a Bitcoin hash only needs 61 rounds instead of 64?

I find it amusing people are comparing a non released product to something that is already operating and outputting real world numbers.

How were you solving the overheat? Liquid nitrogen?

On their website, they state:
Then after choosing serial round design it was very challenging to fit it exactly into 240 slices (8 x 32 area). As you see in snapshot image on the left, magenta color shows exactly two SHA256 rounds location. These double-SHA256 with round and round expanders and additional control logic fits into 240 slices. This took another month of development. Fitting in 240 slices was important to obtain good fill of XC6SLX150 right part.

I hate to break the news, but 8 x 32 is not 240. It is 256. At least, where I grew up. 

So, what did they really do? Fit two rounds of SHA-256 into 240 slices, including control logic? I find that hard to believe.
Or fit two rounds of SHA-256 into 256 slices - I find that slightly easier to believe, but it still would be a major achievement.

Any word yet if the low end -7 series will have metal heatspreader.  I would imagine you could get 20 to 30 Mhz more out of the Spartans if it like trying to pull that heat through the low conductivity plastic package.

Although the parts may not be very modern, the ideas and things surrounding it are very relevant and fun to discuss. Theoretically if designed correctly, it should be possible to replace all the little FPGA modules with 28nm models when those come along, or even specially designed ASICs.