Title says it almost all. I want to get CZK or HUF cash. I will pay in USD or BTC. I would like to meet in person in the Los Angeles area either today Thursday or Friday to do the exchange. I am looking to get the equivalent of 200-400 USD of these currencies. PM or email me at m.bevand @ gmail.com.

Argh. OP updated again.

The Block Erupter 130nm project now claims an estimate of 122 Mhash/Joule: https://bitcointalk.org/index.php?topic=91173.msg1072887#msg1072887

This is such an improvement, that ~500 Mhash/Joule should be possible at 65nm. Combined with the fact that BFL disclosed that Jalapenos will be wall-powered, after all, I think this makes it very, very likely that BFL is developing at 65nm and not 45nm.

OP updated.

I read you too quickly (my bad) and thought you meant 0.5W/2.5W = 20% was the variance. I was denying this.

Yes, ±5% is quite typical for a consumer electronics power spec, and should be implied in all the numbers I quoted, and does not change my point (787 Mhash/J ±5% is still greater than 700 Mhash/J).

No. I have 1 Visiontek (lifetime warranty!) and the rest are Sapphires.

Spec says 500mA, so you can draw 500mA. There is no such thing as "slot variance"; you are making that up...

You would be a pretty bad designer if you needed 0.5W or more to merely power ancillary logic. At most there will be a ~5-10% loss due to the 5V->Vcore power conversion (I doubt the ASIC will run on 5V). The rest (LED) should literally need 0.05W or less. Remember there is no active cooling (it's a coffee warmer). So we are talking about 2.3-2.4W available to the chip.

Try removing the case, and powerping it up. If it still makes a noise, then my solution will not fix it because the noise is caused by something else.

More precisely, scaled to 45nm, Bit Erupter's chip would give 1.96 Ghash/s at 2.5 Watt.
This is 787 Mhash/sec and slightly better(!) than my prediction of 700 Mhash/sec for BFL's ASIC.

No because if you read the specs of the thing you found with 30sec of googling around, you would see the Nitrox III appears to run SHA-2/RSA/etc on RISC cores (ie. a CPU core), which implies it is not a custom SHA-256 ASIC, which explains its poor performance per Joule (after all, if it was an ASIC, it should beat Spartan6 FPGAs, but it does not.)

I said standard cell, not full custom:


And TSCM launched their standard-cell 45nm toolkits 5 years ago! As said earlier in this thread, this is hardly "bleeding edge" tech... The NRE costs are mostly proportional to the complexity of the chip you are designing. This is why dead-simple logic blocks (SRAM cells, NAND, etc) are always the first ones to be built at the smaller nodes (eg. 22 nm), whereas complex chips like the A5 lag behind (45 nm). A dumb SHA-256 logic block is much closer to SRAM/NAND in terms of complexity than a SoC like the A5. So I think BFL doing 45nm is absolutely plausible. But again, as I said in the OP, they may even get away with 65nm.

You write your own miner and properly optimize it to exploit the performance of the GTX 680

Actually I estimated here that the GTX 680 should be theoretically capable of 300-475 Mhash/s (it still sucks compared to AMD GPUs though).

I gave you the answer already: what is consuming the bulk of their 20W power is the other logic blocks such as the RISC cores, RSA engines, etc. That's why comparing such a complex chip like the Nitrox III to a barebone SHA-2 logic block is a pointless apples vs. oranges exercise.

Maybe you should tip Cavium that by taking an open source SHA-2 VHDL design from students/professors, and implementing it on a 12-year-old 130nm design, they could increase their energy efficiency by a factor 49x from 1.45 Mhash/J to 71 Mhash/J.

My point is: obviously Cavium did not aim at SHA-2 energy efficiency. You are comparing Apples vs. Oranges.

Apples vs. Oranges.

Nitrox III implements much more than SHA-2: full-blown RISC cores, RSA acceleration, etc, blowing its TDP up.

30Gbps corresponds to 29 Mhash/s. At 20W that's 1.45 Mhash/J. Nitrox III is handily beaten by all the Spartan 6 FPGAs around here doing 20 Mhash/J. Why were you thinking that Calvium's chips were the "state of the art" in SHA-2 performance?

My point, and rjk's point is that: What makes you think the authors of that paper are the world's best ASIC designers? They are not. They are students and professors. The bleeding edge of ASIC research happens in the professional world (at TSMC, Intel, etc), not in the academic world.

The authors did not need to be excellent ASIC designers to conduct this research. They merely tried to make an average design, and that's all they needed to fairly compare the efficiency of different hash functions. This was all they needed to reach their research goal.

That team achieved 71 Mh/J at 130nm, using standard-cell tech. The true best ASIC designers would have achieved higher that that, using full-custom tech not standard-cell, and would have demonstrated it on a smaller process node like 45nm.

PS: the Virginia Tech researchers did not even do the VHDL design themselves, they implemented the one from GMU: https://cryptography.gmu.edu/athena/index.php?id=source_codes  It looks like it is https://cryptography.gmu.edu/athena/sources/2011_10_01/basic/SHA-2_basic.zip  -> any half-decent ASIC designers should be able to take it, implement it to 45nm standard-cell tech, and get 700 Mh/J

I have explained many times I think they will do 700 Mh/J, not 1750 Mh/J. Read this thread.

$430 for a single card.
$820 for two cards.
Beyond that I can't quote you because the price calculation tool on ups.com is not working (grrrr...)

The round "2 W" number quoted for the Z510 is likely Intel rounding up.
Compare instead the (faster) 1.3 W Z600 which I linked above.
130nm->45nm predicts a reduction of the power to 12% (1/8th), and the Z600 reduces it to 11%, hence proving my point.

Bump.