OP's numbers look plausible.

We established in other threads that current miners are unable to fully exploit the theoretical performance of the GTX 680, so the chip must not be running at "full load", hence the low 100W power consumption.

...and they do:

0.65W Atom Z500 with twice the cache than the Pentium III, more instructions supported (SSE2, SSE3), twice the threads, not 1GHz but close: 800MHz (because it is not 32nm, but 45nm): http://ark.intel.com/products/35472

Or look at this one:
1.4W Atom Z600 with twice the cache, SSE2, SSE3, twice the threads, and 1.2GHz: http://ark.intel.com/products/49656

What do you think Atom CPUs are? They are built upon the Pentium III/M design. Yeah they don't support OOO execution for whatever reason (artificial market segmentation between Atom and higher-end CPUs, or making TDP room for supporting things Intel deemed more important such as 512kB cache, SSE2, SSE3, etc), but they pretty much prove that a sub-Watt (at 32nm) or ~1.5W (at 45nm) Pentium III core is possible.

Which escrow service, for my information?

I too want to know the answer of this.

This is math. Power consumption varies with the square of the feature size. So when comparing a chip designed at 45nm to a 130nm version of it running at the same frequency and same voltage, there should be a 8x better power efficiency: (130/45)**2 = 8.3

Ask your dad, he will tell you that for 2 identical designs, power consumption will vary proportionally to the transistor junction area.

Do you think that Intel having, say, 5 different combinations of core counts, cache size, etc for their Sandy Bridge processors, mean that they incurred 5x the NRE costs to develop them?

No.

They take pre-designed logic blocks (cores, cache, etc) and can mix and match them relatively easily to produce a die with specific characteristics. The few cases where different SKUs are built on the same design (eg. a 3-core CPU made from a 4-core die) allow processor manufacturers to keep a stock of the same die, and "brand" them on-the-fly to match market demand (so that they don't get stuck with unsold 4-core inventory and production capacity when the markets buy 3-core).

For the same reason, BFL designing 2 different dies will not double their NRE cost. It makes sense for a Bitcoin ASIC to be made of the same hashing logic block duplicated dozens/hundreds of times across the die (see the "sea-of-tiny hashers" design made by bitfury -- the same applies to FPGAs). Therefore there is almost zero engineering effort and cost in taking a working die with, say, 60 hashing blocks, and deciding to produce a smaller die with only 10 hashing blocks.

See https://bitcointalk.org/index.php?topic=96165.0

So you did not see the pirate.

I had a hunch he would not show up...

Or insert screw washers: https://bitcointalk.org/index.php?topic=96165.0

Some BFL Single units make a rattling noise. This is in the majority of the cases caused by the smaller fan (enclosed in a copper/silver heatsink) that is touching the case. One very easy solution to fix the problem is to insert 4 screw washers between the bottom standoffs and the bottom side of the PCB, in order to increase the headroom between the fan and the case. I myself fixed 3 of my 10 units this way:



I can sell you some washers since I have plenty extra. Email me at m.bevand@gmail.com. I can mail (US only) 8 washers (enough for 2 singles) for 1 BTC.

Yes. Always been a solo'er since the very first day.

At 250-275 Mh/s per FPGA, I presume you designed it using the "sea-of-tiny hashers" model, like bitfury did. If that's the case, good work! I wonder why not more people try to implement this obviously superior implementation (/me looks at the Cairnsmore1 devs...)

Best guess:
50 chips of 20 Ghash/s each in the Mini Rig
2 chips of 20 Ghash/s each in the Single
1 "small" chip of 3.5 Ghash/s in the Jalapeno which has roughly 1/6th the die size (therefore 1/6th the performance) of the other chips

BFL's claims are plausible at 45nm, not 28nm. See post above.

1440W is a good assumption! This number matches almost exactly my OP which estimates the Jalapeno at 700 Mh/Joule by using 2 USB plugs for power.
This 700 Mh/Joule number makes so much sense that it has become my best bet as to what the SC product line will produce.
700 Mh/Joule is even doable at merely 45nm per my OP.

• Jalapeno SC: 5W via 2 USB plugs, 3.5 Ghash/s -> 700 Mhash/J
• Single SC: 57W, 40 Ghash/s -> 700 Mhash/J
• Mini Rig SC: 1440W, 1 Thash/s -> 700 Mhash/J

Neither. It talks about SHA-256 speed in Gbit/sec. See "Note 1" in my first post.

Except you just increased your cost per Mh/s by a factor 1000x.

This is why GPUs cannot compete with FPGAs even when underclocked/undervolted. Because you still pay full price and end up running the hw at a fraction of the speed it is capable of.

Let me ask you this: if the chip measured 13.76 mJ/Gbits at 130nm, what do you think is a plausible mJ/Gbits performance figure at 32nm? how about 45nm?

I know. (Actually 1400 Mhash/Joule at 2.5W.) And the goal of this thread is to compare BFL's theoretical claims vs. actual chips.

This thread shall be used to report the best demonstrated energy efficiencies of real-world ASIC implementations of SHA-256 at the chip level.

• 1290 Mhash/Joule claimed by bitfury at the chip level, and 1140 Mhash/J were confirmed by cscape at 12V.
• 310 Mhash/Joule as reported by BFL on their 65nm ASIC (they document 3.2 Watt per Gh/s).
• 167 Mhash/Joule as reported by Bitfountain/ASICMINER/friedcat when measuring power consumption on their Block Erupter 130nm ASIC (down to "6 Watt per 1 Ghash/s"). At 12V DC their implementation's efficiency is 130 Mhash/Joule (each 10.752 Gh/s blade consumes 83 Watt). Note that previous RTL simulations had estimated 238 Mhash/Joule at the chip level.
• 151 Mhash/Joule for the 110nm Avalon, as advertised by the vendor saying 6.6-6.7 Watt per Ghash/s and as confirmed by real-world measurements (620 Watt at the wall but 438 Watt consumed by the chips after removing AC/DC and DC/DC PSU inefficiencies).
• 73 Mhash/Joule derived from "13.76 mJ/Gbits" as measured on a 130nm ASIC developed by a research group from Virginia Tech for comparing SHA-256 to SHA-3 candidates: http://rijndael.ece.vt.edu/sha3/publications/DATE2012SHA3.pdf (pub. March 2012). RTL simulations preceding the manufacture of the chip had predicted a number very close to this: 13.42 mJ/Gbits.

(Note: for reference, hashing 1 gigabit of data per second corresponds to a mining speed of about 1 Mhash/s because one Bitcoin hash consists of hashing 1024 bits of data, or 2 SHA-256 data blocks: SHA-256(SHA-256(x)) minus a few SHA-256 steps that can be optimized out.)


BFL claims the 'SC' Jalapeno (3.5 Ghash/s) will be USB-powered. I theorize it will draw 5W via 2 USB ports (2.5W per port), giving it an efficiency of 700 Mhash/J. Edit: BFL has since then confirmed that the Jalapeno will be powered by 2 USB ports.

The 167 Mhash/J number at 130nm indicates that 668 Mhash/J should be possible by merely scaling down the design to 65nm (because 65nm is theoretically 4x more power efficient than 130nm as efficiency is linearly proportional to the transistor junction area), confirming my BFL estimate of 700 Mhash/J. Furthermore, it is known that BFL pre-sold $250k of SC devices in the first day, making it almost certain that they can cover the NRE cost for developing at 65nm which is only $500k. (And on top of pre-order revenues, BFL also claim to have received VC capital.)