Bitfury: "16nm... sales to public start shortly"

[RoadStress]

You completely forgot about SSN (Simultaneous Switching Noise).

The Enterpoint's Cairnsmore is the best example. It was designed by a professional FPGA board designer, yet it failed to properly distribute clock from single Spartan 3 array controller to the four Spartan 6 mining chip. The guy who finally developed a working bitstreams had to do a lot of trial & error before he managed to squeeze the competitive output from that board. The competing 1.15y board from ZTEX did not exhibit those problems.

Even a simple, but regular and symmetric multichip design can produce hard to suppress resonances.

I applaud sidehack & friends for being careful. If they don't already have access to the appropriate analog models and software it is a very good decision to produce small and conservative design at first.

Edit: Being conservative is especially important with the attitude towards the interator designers exhibited by Bitfury and especially punin in the nearby thread. I presume that Bitfury doesn't even have proper IBIS models that would facilitate high-performance board design.

Careful! You might be approached for a collaboration...

[NotFuzzyWarm]

Yes if you see any "snake" type traces its because they are parallel IO traces to some other longer traces, so they need to make the traces the same lengths hence the snakes. If you check out your PC motherboard you'll see them all over the place on the PCIe and RAM lanes. When your talking about throughputs in the muti Gigabits/s even the speed of light works against you

This does not matter on anything bitcoin related though, since these are very dumb chips IO rates coming to/from them are in the order of sub 1Mb/s, since nothing larger than a couple hundred bytes is ever sent to the chips( and return IO is even less...just an 8 byte nonce return and maybe a few bytes of chip info data).

You completely forgot about SSN (Simultaneous Switching Noise).
<snip>

Exactly. As in point 3 of http://powerelectronics.com/power-electronics-systems/five-things-every-engineer-should-know-about-pdn
 "Low rates have higher probability of issues

While it might appear that the higher the signal frequency, the more prominent the PDN issue might be, this is not always the case. The increased signal frequency certainly does carry with it an increase in signal integrity concerns, but not necessarily for the PDN. "

If the lines are long I'd want to see guard traces between each of the address and data lines running together. Short lines, say just a couple inches should be good but if np to have them there - do it.

As for the PDN itself it is a matter of the buck regulators switching freq vs the low speed coms. A buck will typically run between 50-250kHz, switching spikes from low speed coms can easily fall into that range if not looked after.

Good part is that the lit on the BitFury website for the 16nm chip says that all the needed supply bypassing is already present inside of the chip package so hopefully that will never be an issue when using the BitFury chips

[NotFuzzyWarm]

'Prolly should say that my extreme conservative approach to pcb layout comes from first making boards using tape on Mylar then cut Rubylith  back in the 60's through pretty much the late 80's, virtually all analog from damn near DC through RF. You learn fast to be up on best-practices eg. Be Damn Careful and never assume - verify it.

When them durn newfangled PC's showed up and eventually combined with photoset machines for making the layout masks it made correcting problems/errors a lot less painful... Nowadays, just get a 4-board proto run from PcbExpress or whoever and not bad at all to make changes. But Lessons learned stick.

My favorite and now deceased columnist who perfectly mirrors my views on the electronics design process http://electronicdesign.com/author/bob-pease
Pay special attention on using sims like Spice. eg, how-to and how not-to.

His works should be mandatory coverage in any EE program.

[2112]

'Prolly should say that my extreme conservative approach to pcb layout comes from first making boards using tape on Mylar then cut Rubylith  back in the 60's through pretty much the late 80's, virtually all analog from damn near DC through RF. You learn fast to be up on best-practices eg. Be Damn Careful and never assume - verify it.

When them durn newfangled PC's showed up and eventually combined with photoset machines for making the layout masks it made correcting problems/errors a lot less painful... Nowadays, just get a 4-board proto run from PcbExpress or whoever and not bad at all to make changes. But Lessons learned stick.

My favorite and now deceased columnist who perfectly mirrors my views on the electronics design process http://electronicdesign.com/author/bob-pease
Pay special attention on using sims like Spice. eg, how-to and how not-to.

His works should be mandatory coverage in any EE program.

This is only one side of the coin. But this coin has two sides. I believe that no amount of breadboarding or soldering would lead to things like https://en.wikipedia.org/wiki/Chua%27s_diode, https://en.wikipedia.org/wiki/Chua%27s_circuit and https://en.wikipedia.org/wiki/Memristor .

He is also the inventor and namesake of Chua's circuit one of the first and most widely known circuits to exhibit chaotic behavior, and was the first to conceive the theories behind, and postulate the existence of, the memristor. Twenty-seven years after he predicted its existence, a working solid-state memristor was created by a team led by R. Stanley Williams at Hewlett Packard.

But lets be realistic. This is a Bitcoin mining board. Here people who never attempted to plug Type-A USB into Ethernet RJ-45 socket are considered computer experts.

Try it, they'll fit and won't break. I challenge you.

[NotFuzzyWarm]

'Prolly should say that my extreme conservative approach to pcb layout comes from first making boards using tape on Mylar then cut Rubylith  back in the 60's through pretty much the late 80's, virtually all analog from damn near DC through RF. You learn fast to be up on best-practices eg. Be Damn Careful and never assume - verify it.

When them durn newfangled PC's showed up and eventually combined with photoset machines for making the layout masks it made correcting problems/errors a lot less painful... Nowadays, just get a 4-board proto run from PcbExpress or whoever and not bad at all to make changes. But Lessons learned stick.

My favorite and now deceased columnist who perfectly mirrors my views on the electronics design process http://electronicdesign.com/author/bob-pease
Pay special attention on using sims like Spice. eg, how-to and how not-to.

His works should be mandatory coverage in any EE program.

This is only one side of the coin. But this coin has two sides. I believe that no amount of breadboarding or soldering would lead to things like https://en.wikipedia.org/wiki/Chua%27s_diode, https://en.wikipedia.org/wiki/Chua%27s_circuit and https://en.wikipedia.org/wiki/Memristor .

He is also the inventor and namesake of Chua's circuit one of the first and most widely known circuits to exhibit chaotic behavior, and was the first to conceive the theories behind, and postulate the existence of, the memristor. Twenty-seven years after he predicted its existence, a working solid-state memristor was created by a team led by R. Stanley Williams at Hewlett Packard.

But lets be realistic. This is a Bitcoin mining board. Here people who never attempted to plug Type-A USB into Ethernet RJ-45 socket are considered computer experts.

Try it, they'll fit and won't break. I challenge you.

Since this is the place to be free to wander a bit, No doubt sims/tools are needed these days. However, even running a logic sim through an FPGA does not mean the on-silicon equiv will work right. <holds up picture of the A1> By what the archived A1 Dev site says, Zeffir  had it working perfectly on his FPGA rig. Come Inno's first engineering sample chips and bzzzt...Power & freq specs way off.

Pease's topic http://electronicdesign.com/analog/what-s-all-spicey-stuff-anyhow-part-25 emphasizes that tools are only as good as the (known or all too often assumed ) data and conditions fed in. They definitely have their need but: Ya know - GIGO.

Now is my (conservative) approach overkill? Well for Consumer grade electronics probably so. <yes> We still support several systems I personally built in the late-70's. They still run 24x7x365 making parts for chips and other things in the everyday world around us. So ja, I do overkill a bit...

On USB-A/RJ-45... or if <cough> someone is trying to reach around the back of a PC to plug one in. Ya know 4 of them are right around... next to the RJ....

[kilo17]

This is a Bitcoin mining board. Here people who never attempted to plug Type-A USB into Ethernet RJ-45 socket are considered computer experts.

Try it, they'll fit and won't break. I challenge you.

I tried to stick it into everything when I was 16, now I am >40 (and married) and know exactly where it needs to go.  No more sticking it in the wrong place

[Mitak]

I'm 40+ too but still have troubles with the right target for sticking

[sidehack]

Hey man, accidents happen when you can't see what you're working on.

[Finksy]

Any reacharounds are a bonus in my books

[NotFuzzyWarm]

Just tossing this rather interesting idea out there for general cogitation.... http://www.ecnmag.com/news/2015/10/liquid-cooling-moves-chip-denser-electronics

[sidehack]

Better hope you don't snap off the nipple or you'd have to replace the whole board.

Also, temperatures 60% lower is a really bad way of saying what they're trying to say. 60% lower temperature from, say, 60C is about -140C if you define temperature properly.

But, interesting.

[Biodom]

I understand that this might be wholly irrelevant since this project will soon have standard ASIC chips (Bitfury?), but here is something interesting about the approximate mining.
http://bravenewcoin.com/news/approximate-mining-could-increase-bitcoin-mining-profits-by-30-percent-research-shows/

Not sure if it was already discussed. If yes, ignore and I will delete this post later.
I wonder if this has to be implemented on a chip+software or could be some additional circuit that provides the adder that they described =Kogge-Stone Adder (KSA).
Apparently, the result is ~30% hashing speed gain.

[CjMapope]

I understand that this might be wholly irrelevant since this project will soon have standard ASIC chips (Bitfury?), but here is something interesting about the approximate mining.
http://bravenewcoin.com/news/approximate-mining-could-increase-bitcoin-mining-profits-by-30-percent-research-shows/

Not sure if it was already discussed. If yes, ignore and I will delete this post later.
I wonder if this has to be implemented on a chip+software or could be some additional circuit that provides the adder that they described =Kogge-Stone Adder (KSA).
Apparently, the result is ~30% hashing speed gain.

i saw that. i was reading  http://rakeshk.crhc.illinois.edu/dac_16_cam.pdf     
very interesting indeed, tho above my personal "tech grade" haha  (tho threads like this help with that ;p)

[brontosaurus]

I understand that this might be wholly irrelevant since this project will soon have standard ASIC chips (Bitfury?), but here is something interesting about the approximate mining.
http://bravenewcoin.com/news/approximate-mining-could-increase-bitcoin-mining-profits-by-30-percent-research-shows/

Not sure if it was already discussed. If yes, ignore and I will delete this post later.
I wonder if this has to be implemented on a chip+software or could be some additional circuit that provides the adder that they described =Kogge-Stone Adder (KSA).
Apparently, the result is ~30% hashing speed gain.

This paper is a load of garbage. SHA256 is not an algorithm that tolerates 'approximation' which, if the writers had bother to do their research, they would have realised very quickly. Every bit at every stage is cucial, you can't just leave ones out that you think don't matter.

What they may have been meaning is that by using different types of adder in the A and E calculations the die size could be made smaller, but at lot of folks got this message a long time ago.

[2112]

This paper is a load of garbage. SHA256 is not an algorithm that tolerates 'approximation' which, if the writers had bother to do their research, they would have realised very quickly. Every bit at every stage is cucial, you can't just leave ones out that you think don't matter.

What they may have been meaning is that by using different types of adder in the A and E calculations the die size could be made smaller, but at lot of folks got this message a long time ago.

C'mon, brontosaurus, think before writing. SHA256 by itself doesn't tolerate any approximation, but Bitcoin mining does tolerate high error rates very well.

This paper isn't "garbage". It is just "publish or perish" tripe. Somewhat more calm review of this paper done by me about two weeks ago:

Sergio Demian-Lerner has discussed this in February of 2015 on his blog:

https://bitslog.wordpress.com/2015/02/17/faster-sha-256-asics-using-carry-reduced-adders/

Basically it is an interesting idea, but neither Sergio nor those 3 guys discussed how it could be affected by the overall pipeline design. It seems like those guys from UIUC considered only one (or maybe two) pipeline layouts (the alternate drawn in dashed lines).

Much better science would be to consider way more pipeline layouts including something extreme like 32-way pipelined ripple-carry-adder that adds two 32-bit integers in 32 clocks. It seems slow, but the area is unbeatable. At least those guys explicitly discussed area*delay products. But it doesn't seem like they carried this to the ultimate conclusion of power/hash rate and area/hash rate (or better yet price/hash rate).

But it is the only paper that I've seen that was actually brave enough to include the plain ripple-carry-adder (RCA) in the final comparison tables and graphs.

[tmfp]

This thread is really interesting for me, not being a tech head but willing to learn.

But back to the actual title of the thread "Bitfury: "16nm... sales to public start shortly"....

I was listening to this https://soundcloud.com/heryptohow/roger-ver-vs-joby-weeks-sasha-daygame-juan-galt-jeff-berwick

BitClub Network are an MLM funded mining operation, they have a pool with currently just under 40 PH/s, somewhere around 4% of the total.
The conversation on the audio came about because BCN promoters were using Roger Ver's name in their material, and he got a bit pissed about that.

A person called Joby Weeks represents BitClub Network, altho a formal position in the operation is unclear.
In it, he makes several claims of relevance to this thread.
I wonder what your thoughts are, especially punin's, as Weeks' claims flatly contradict what he has been saying.

What say, punin?

Some of Weeks' claims (transcribed by me, 99% word for word, check them yourselves)

"I've got the new (Bitfury) 16nm tech chips"

"BCN are the only people in the world with Bitfury chips, buying all they can produce."

We've got 12 PH/s Bitfury containers

buying $17million of Bitfury containers at $3m a piece

Also, BCN has increased mining capacity by double since 22nd Jan, referring in their pool to

bitclubfury940.bf

And just for luck, although not Bitfury related, he (BCN)

pays Bitmain $100 for an S7

I have been following the progress of BitClub Network here

[dogie]

And just for luck, although not Bitfury related, he (BCN)

pays Bitmain $100 for an S7

I have been following the progress of BitClub Network here

Not a chance.

[sidehack]

I'd guess material cost is at least $200 for an S7.

[alh]

If BCN were getting S7's for $100, they could make way more money by selling them for $400, and not need to worry about their facilities costs or BTC price.

The $100 price seems REALLY improbable......

[RoadStress]

The $100 price seems REALLY improbable......

Meanwhile a container at $3M seems really plausible!