Bitfury: "16nm... sales to public start shortly"

[sidehack]

If I was looking for a slick salesman to make me empty promises, I wouldn't be asking someone whose opinion and technical expertise I trust. I'm not looking for a guaranteed win at anything. I'm asking if something could be possible and what it might cost to pull off. If you say it can't be done, I'll drop it. If you say it might be possible but not worth the money, I'll drop it. If you think there's a chance it's possible with the right people working on it, maybe I'll start looking for those right people. I don't want salesmen and I don't want monkeys.

The difference between me and someone who gambles on horse races is, I hate gambling and would rather be the horse. Sorry if that freaks you out.

[irritant]

I'll put my money on sidehack 

[2112]

If I was looking for a slick salesman to make me empty promises, I wouldn't be asking someone whose opinion and technical expertise I trust. I'm not looking for a guaranteed win at anything. I'm asking if something could be possible and what it might cost to pull off. If you say it can't be done, I'll drop it. If you say it might be possible but not worth the money, I'll drop it. If you think there's a chance it's possible with the right people working on it, maybe I'll start looking for those right people. I don't want salesmen and I don't want monkeys.

The difference between me and someone who gambles on horse races is, I hate gambling and would rather be the horse. Sorry if that freaks you out.

I think it is possible, even fairly easily, without big money outlay. You just need to find somebody familiar with the proper design flow: mixed signal, analog or high-power. Mining chip designed through a run-of-the-mill low-power digital design flow will be rather inefficient because such they assume too low tolerable error rates and too low internal temperatures and switching noise levels.

You'll be best served not by doing standard merchant-commercial fabrication/production but a prototype/research/educational fabrication through MOSIS or Europractice. (for their first chip Bitfury partnered with some small Polish research institution to be eligible for Europractice prices.) Therefore you can summarily ignore all price quotes from this forum, because they were standard merchant terms.

I'm familiar with the relevant design flow, but my experience and my tools are badly out of date for the modern deep-submicron design flows and tools. I also don't want to be like that Boxer horse in Orwell's Animal Farm,  I know that the sweat capital is nearly worthless in semiconductor design and manufacturing. I'm not an expert, but I know the rules of the game well enough to avoid gallant and valiant efforts that are guaranteed failures.

The other handicap you will be facing is that the Bitcoin mining chip design field is unfortunately mostly populated with crackpot wannabes with less than zero experience. How one could get less than zero experience? There are apparently many fraudulent educational institutions offering "chip level repairing" courses. Please google the the term, I don't want to give explicit URL links to some of the "Expert Laptop Repair Training Colleges". So when you are going to contact the actual practitioners in the ASIC field be aware that they were probably already contacted several times by various crackpots. You'll have to be able to show from the start that you did your homework and have some understanding of the reality, not just the bullshit from the sales brochures. You can't afford to ask stupid questions. Make sure that the questions you ask are sane. Don't ask ASIC designer for a chip in QFN package, because you make yourself look like a prospective car buyer that asks "can I get it in darker shade of grey to match my poodle?"

[sidehack]

Thanks for the advice. Several things there (and in previous replies) that I hadn't considered. I now know more than I did, so thanks.

I only have a conceptual knowledge of semiconductor design, no practical experience inside an IC package or, to be honest, even FPGA design. Most of my job is board-level design and... well, actually the bulk of my job right now is board-level manufacture of the things I've designed. Guess I'll have some reading to do and other smart people to talk with.

And hopefully someone someday gets back about Bitfury chips.

[2112]

Real, no bullshit, prices from slightly out-of-date Europractice access to GlobalFoundries 22nm process:

50 prototype dies, unpackaged, untested

48,000EUR for up to 3mm² plus 16,000EUR per each additional mm².

I'm not up to speed, but by my understanding is that access through MOSIS (sidehack is based in the USA) is both slightly cheaper and has somewhat more frequent shuttle runs.

A young, personable individual could do the tape out for free by pretending to audition some EE courses in some local (US or EU) school that has the required CAD/toolchain available in the student's labs. I remember from my student days several groups of people that manufactured prototypes on the side while taking courses. The only time my school objected/prosecuted was when some lamers actually physically took the test equipment out of the lab (in effect stealing). Many people overbooked the computer lab time in ridiculous amounts to run side consulting jobs.

Good luck to you, sidehack, personally.

[PlanetCrypto]

Since it's obvious I couldn't find my ass with a map in the chip fab world, how about clarifying a couple of things:

50 prototype dies, unpackaged, untested

"unpackaged" means the bare die with no carrier? right?

48,000EUR for up to 3mm² plus 16,000EUR per each additional mm².

"3mm²" is the die size?

What is "... the required CAD/toolchain" to design (tape out?) something like sidehack was proposing?

We, as a company, have a couple of other chip concepts outside the crypto currency world.
If the cost of the S/W isn't to prohibitive and we knew what we were looking for/pricing we might spring for it.

Thanks in advance.

[sidehack]

I still live in the town where I went to college (Rolla is home to one of the best engineering universities in the central US), in part because I ran out of money before finishing school (y'all know how much I hate borrowing). If some plans I have in place right now work out, I should be able to finally get back in this fall and finish up in one or two semesters part-time. I'll see what classes they have on VHDL when I'm talking to enrollment folks this coming week.

Also, possible this line of discussion should shift over to the Community Miner thread, since - and yes I know it's my fault - we're tangented pretty far off topic now.

[2112]

Since it's obvious I couldn't find my ass with a map in the chip fab world, how about clarifying a couple of things:

"unpackaged" means the bare die with no carrier? right?

"3mm²" is the die size?

What is "... the required CAD/toolchain" to design (tape out?) something like sidehack was proposing?

We, as a company, have a couple of other chip concepts outside the crypto currency world.
If the cost of the S/W isn't to prohibitive and we knew what we were looking for/pricing we might spring for it.

Thanks in advance.

You won't like my answer, but I have to reiterate what I wrote in response to sidehack. You can't afford to ask stupid questions. If you behave like a time-wasting crank, people will treat you like a crank or crackpot. Both MOSIS and Europractice don't have funds to employ salesforce that could tolerate such inquiries. It is presumed that the prospective customer of theirs is sufficiently intellectually inquisitive to read information on their websites.

Europractice serves only European countries plus some culturally related territories, like ex-Euro colonies or ex-USSR. PlanetCrypto is based in US, so you will only qualify for MOSIS. I referred to Europractice partly because of my background and partly because more of the Europractice's site is available for non-members, before signing off the NDA.

[2112]

I'll see what classes they have on VHDL when I'm talking to enrollment folks this coming week.

And pray tell, how would learning VHDL help with developing efficient ASIC mining chip? How that thought popped in your mind?

Also, possible this line of discussion should shift over to the Community Miner thread, since - and yes I know it's my fault - we're tangented pretty far off topic now.

Or we could maybe invoice Bitfury for shilling services in their thread?

[sidehack]

If I'm thinking right, VHDL would get me FPGA design, which is probably a good place to start making sure I at least know how to do the basics right with some real-world implementation. It wouldn't directly help me build anything ASIC but it'd be a start. I'd like to have more of a foundation to build on.

[2112]

If I'm thinking right, VHDL would get me FPGA design, which is probably a good place to start making sure I at least know how to do the basics right with some real-world implementation. It wouldn't directly help me build anything ASIC but it'd be a start. I'd like to have more of a foundation to build on.

This looks like you want to have career as a CAD monkey at a defense contractor. In the USA VHDL is mostly used by those who are paid by Department of Defense (VHDL being an offshoot of Ada, also sponsored by DoD). The civilian industry mostly uses Verilog.

Anyways, learning VHDL or any other hardware description language emphatically isn't learning foundations. This is just a front end, one of many ways of inputting the design into the design workflow. If you have solid foundations, you could pick up VHDL, Verilog, SystemC or any other language in about a week or two of full time work (8hrs/day 5days/week). I know I did just that at my first job. Within first month I started filling bugs against the VHDL compiler (they were quite immature then.)

Overall, learning such a shallow stuff like would be a waste of time and money at a college for somebody who is already working and not looking to extend his childhood. To make the college costs worthwhile you'll need to make their enrollment/intake people really work for you. Here's how to do it properly (I'm assuming that your educational goal is to learn how to design a really good Bitcoin mining ASIC).

Don't mention Bitcoin. Mention the following problem: I have a 28nm ASIC in which the critical path is in the expression temp1 := h + S1 + ch + k(i) + w(i), all values being 32-bit registers. This ASIC works at about 300MHz. On the other hand I know that Intel CPU could execute instructions like mov eax,[ebx+4*esi+offset] at a rate of about 3GHz when still using about 100nm process (Pentium 4 a.k.a. Netburst). There are only two visible additions in the Intel instruction, but more are hidden in the segmentation/paging/caching hardware. I don't want to compete with Intel, I just want to learn how to make my little ASIC run at a real competitive speed. Can your school teach me something that would help me achieve this goal?

I don't know the admission process in your school, is it just a single administrative person or are you going to face an admission committee consisting of a mix of administrative and teaching faculty people? You may also want to visit your school on some "open days" and talk to the prospective professors.

Your original idea (asking for VHDL course) looks exactly like you were trying to fit yourself into some job posting from a defense contractor. It is your life and I can't tell you what to do with it. But in my opinion focusing on minutia is a wrong way to pursue education.

[sidehack]

Fair enough, that's just the descriptor language I know exists and we touched on it a bit in a class some years back. I'm not really sure who I'll have to talk to about admissions, but I'll be on campus one day this week to get the ball rolling. I've already put in six years there (ending six years ago), where I ran out of money about a semester shy of completing degrees in Computer Science, Computer Engineering and Electrical engineering with minors in math and writing (and about half a physics minor). So there's a lot I know something about but nothing I know everything about, and chip design innards (or the languages and toolchains required) is something I hadn't looked at at all.

I don't really have a 40-hour week to sit down and do anything. I'm already at work about 65 hours a week as it is, not counting when I take work home, and sometime in there I have to handle meals and household stuff. Maybe sometime in June, if I'm between manufacturing batches, I'll have time to hammer on it.

[Mr. Kashif]

Does anyone have any updates from bitfury regarding their chips?

[one4many]

Does anyone have any updates from bitfury regarding their chips?

Some ol' some ol'

... Announce an unrealistic timeline ... OR ... promise heaven on earth (tomorrow)  
... Stir the PR pod pood  
... Become very silent  
... release (if ever) with massive delays  

All because of (EVIL) world happening.  

Just wait and see  

    one4many

[HyperMega]

Since it's obvious I couldn't find my ass with a map in the chip fab world, how about clarifying a couple of things:

50 prototype dies, unpackaged, untested

"unpackaged" means the bare die with no carrier? right?

Yes, bare silicon dies in gel-pak.

But if you go for a standard package, prototype packaging service is also available:
http://www.europractice-ic.com/prototyping_packaging.php

Don't be scared, in volume production the packaging per sample is much cheaper.

48,000EUR for up to 3mm² plus 16,000EUR per each additional mm².

"3mm²" is the die size?

Yes, but this is not much for a mining ASIC even in 22nm. I guess it should equate to about 10 ... 15 unrolled hash cores, because this 22nm GF node is only a 80% shrink of the GF 28nm node, not a true 50% shrink like other 20nm nodes. But therefore the 22nm masks cost only a little bit more than a 28nm mask set.

What is "... the required CAD/toolchain" to design (tape out?) something like sidehack was proposing?

You have the choice

www.synopsys.com
www.cadence.com
www.mentor.com

You need a bunch of these tools and people, who know how to use them.

In general EDA tools for advanced nodes are very expensive ("big problem, small market"). A complete full+semi custom tool-set for a small design team will cost you at least $500k per year.
And yes, Universities have these tools almost for free, but for strictly non-commercial use. As soon as you want to design something, which could be commercialized directly or indirectly it is illegal to use University licenses for it. If something like this would be discovered by the EDA vendors, you and the University would have huge problem.

We, as a company, have a couple of other chip concepts outside the crypto currency world.
If the cost of the S/W isn't to prohibitive and we knew what we were looking for/pricing we might spring for it.

Thanks in advance.

If you like to get your feeds in the water here, it would be better to cooperate with a IC design service company at least for the first project. You bring the chip concept and architecture, they help you to design, manufacture, package and test it.
From my point of view, it is almost impossible to build up the required competences from scratch, despite you hire some experienced IC designers in your company.
Where is your company located?

[eldentyrell]

Europractice serves only European countries plus some culturally related territories, like ex-Euro colonies or ex-USSR. PlanetCrypto is based in US, so you will only qualify for MOSIS.

That is definitely not true.  I have a chip I designed and fabbed through Europractice sitting in front of me right now and neither I nor my company have any connection to Europe.

For a while TSMC would not let them quote US customers, but that restriction was for that one fab only and it has since been removed.  The only thing Europe-only is the academic discounts.

Europractice's IMEC team in Belgium (the ones who do UMC+TSMC tapeouts, but not GF) are absolutely top-notch, outstanding people.

[NotFuzzyWarm]

Hypermega: Thank you for a very useful reply to Sidehacks questions vs the snarkasim from 2112. Needing to ask questions about things outside of ones core competency is not a bad thing and should be met with better than Ivory Tower attitude.

[brontosaurus]

What I'm asking about is the expected cost of one chip assuming the design works and reaches mass production. I know the NRE cost is going to be a varying factor not just because NRE is highly variable but because it'd be a fixed initial cost divided amongst an unknown quantity of individual chips. It's not that I don't understand or am trying to fool everyone. I want an idea of the forest, not individual trees.

So, to be more precise than I at first assumed I would have to be to make the question clear to intelligent people seeking to assist rather than get into semantic arguments - let's say the goal is to design a 20nm ASIC that gets 0.1J/GH somewhere in its operating range; could be bottom clock. Give it about 10W expected power dissipation, fairly standard QFN package. Does someone who knows more about semiconductor design think that's possible? If so, assuming we want to produce 1 million ASICs, what would be an expected TOTAL COST combining production costs and NRE, and what would be expected purely for production costs?

Just notice your post Sidehack. Nice to see someone thinking laterally but why not make this into a separate thread where it might attract more views and possibly more inputs to your questions?

For my two cents worth, forget about 20nm, it never delivered what it promised but good old 28nm is cheap and stable and there's plenty of design expertise at reasonable cost. As a quick answer to your question, to effectively create a system to give you 1 million 28nm production asic's at around twice the die size as Bitfury's 16nm (40 mm² as against 25 mm² I'm guessing) running at around 100Gh/sec at 10 watts at a 'sweet spot' would take about US$ 7 million, or $7 per chip. Of that around $4 million is for the actual packaged devices, the other $3 million is NRE and design fees. Making 2 million would work out at $5.50 per device. Hope this helps.

[2112]

Yes, but this is not much for a mining ASIC even in 22nm. I guess it should equate to about 10 ... 15 unrolled hash cores, because this 22nm GF node is only a 80% shrink of the GF 28nm node, not a true 50% shrink like other 20nm nodes. But therefore the 22nm masks cost only a little bit more than a 28nm mask set.

This is a perfect example of daft thinking of a CAD monkey. No sane hardware engineer would waste that valuable real estate (50 plots of 3 square millimeters each) to fill it out with identical unrolled cores and try to commercially mine with them. The sane engineer would fill those 3 sq.mm with as many different interesting designs as he/she could think of and then compare simulated results with actual results to gauge the accuracy of the toolchain. That is the whole point of prototyping.

I understand that some people find "CAD monkey" term offensive. But such proposal as above is equally offensive to the normal hardware engineers. That is why https://en.wikipedia.org/wiki/Code_monkey epithet was invented to quickly distinguish a narrow subset of programmers.

And yes, Universities have these tools almost for free, but for strictly non-commercial use. As soon as you want to design something, which could be commercialized directly or indirectly it is illegal to use University licenses for it. If something like this would be discovered by the EDA vendors, you and the University would have huge problem.

This never happens to students or faculty at non-profit schools. It does happen in for-profit schools or maybe at non-profits when administrative staff gets involved in theft or unauthorized resale. In normal schools the https://en.wikipedia.org/wiki/Academic_freedom and https://en.wikipedia.org/wiki/Scientific_freedom will easily trump the short term commercial concerns.
 

If you like to get your feeds in the water here, it would be better to cooperate with a IC design service company at least for the first project. You bring the chip concept and architecture, they help you to design, manufacture, package and test it.
From my point of view, it is almost impossible to build up the required competences from scratch, despite you hire some experienced IC designers in your company.
Where is your company located?

I worked for a while for EDA vendor and I start sensing a sales-critter. I'm the last person to try to blame the sales person for trying to earn the commission. In fact I'm still grateful for being invited the celebratory party of one salesman who with single sale funded (pre-paid) college education of two of his kids.

I also remember particular post trade-show dinner party (in Anaheim,CA or Las Vegas,NV) with various EDA industry bigwigs. One thing I remembered was one founder being asked how he got money to start up. His story was that out of school he was reselling used office furniture.  One time they bid several k$ for a closed office of some major US automotive concern (Ford? can't recall anymore). It turned out that the cabinets were filled with Ford's(?) internal paperwork related to hard-to-fix warranty repair problems. They actually successfully blackmailed Ford(?) into buying those cabinets back for some 1M$.

Why I'm retelling this story? People need to learn how to bargain with EDA vendors. Here's a quick example:

So power consumption variance is +-20%, can we infer the same with hash rate then? Since usually more power  means more heat to dissipate.

Most commonly the power consumption of real silicon comes in better (lower) than the predictions from the Apache Redhawk tool we are using. The cooling system in the Baby Jet is massively over engineered, to give some margin, and to support overclocking.

Cheaply buy out of the bankruptcy the intellectual property that went through that Apache Redhawk simulation with gross errors. Then talk to Ansys https://www.apache-da.com/ to fund a research grant that would establish the reasons for such large errors and ways to correct their products. It is not much of business idea but it is an idea of how to not only get expensive EDA tool for free but also get funding/grant for its use at a research university.

[2112]

That is definitely not true.  I have a chip I designed and fabbed through Europractice sitting in front of me right now and neither I nor my company have any connection to Europe.

For a while TSMC would not let them quote US customers, but that restriction was for that one fab only and it has since been removed.  The only thing Europe-only is the academic discounts.

Europractice's IMEC team in Belgium (the ones who do UMC+TSMC tapeouts, but not GF) are absolutely top-notch, outstanding people.

I'm glad you were able to catch and correct my error. Admittedly I'm nor really familiar with the merchant terms for one-off designs. I always worked either through academia or with the long-term projects that involved purchasing options for masks and wafers.

WIth SHA256D miner isn't any issue of secrecy or intellectual property. Getting into partnership with some academic institution would not be problem at all. That was what Bitfury did with their first chips. Here's a quick example of a subject for a master thesis or a post-doc paper:

Comparison of combinatorial constant-propagation gains versus passive transmission loses through varying unroll factor in digital circuits with high toggle ratio.

That would be about 75% to 90% of work required to optimize a Bitcoin miner ASIC. For particular example Bitfury used unroll factor 2 in his original chip.