But I've already been using RRD = 4 for months because I've been using Stilt's strap. I am going to test both, I just want to know how to modify the output of the tool to change RRD=5 to RRD=4 so I can start testing.

Btw my 290's max mem clock is ~1500 so I probably need tighter than usual timings. The 390s can do over 1625 so they probably need RRD to be higher.

EDIT: nvm I just realized there's a windoze version of the ohgodadecode tool so I'll just check myself.

EDIT2: mmmkay that tool says that TRRD = 0 when i input 77713320000000000839472A50550C0B242045040046C40022BB1C005C0B14204A8900A00000012 0120C211E51192613

I'm guessing it only works for RX timings.

I'm just going to assume my original...uhh...assumption is correct.

It is Correct, indeed:

--> HEX strap: 77713320000000000839572A50550C0B242045040040040022BB1C005C0B14204A8900A00000012 0100C211E51192613

--> MC_SEQ_WR_CTL_D0

DAT_DLY = 7, DQS_DLY = 7, DQS_XTR = 1, DAT_2Y_DLY = 0, ADR_2Y_DLY = 0, CMD_2Y_DLY = 0, OEN_DLY = 7, OEN_EXT = 3

--> MC_SEQ_WR_CTL_D1

DAT_DLY = 0, DQS_DLY = 0, DQS_XTR = 0, DAT_2Y_DLY = 0, ADR_2Y_DLY = 0, CMD_2Y_DLY = 0, OEN_DLY = 0, OEN_EXT = 0

--> MC_SEQ_RAS_TIMING

TRCDW = 8, TRCDWA = 8, TRCDR = 14, TRCDRA = 14, TRRD = 5, TRC = 42, Pad0 = 0

--> MC_SEQ_CAS_TIMING

TNOPW = 0, TNOPR = 0, TR2W = 21, TCCLD = 2, TR2R = 5, Pad0 = 0, TW2R = 12, TCL = 11, Pad1 = 0

--> MC_SEQ_MISC_TIMING

TRP_WRA = 36, Pad0 = 0, TRP_RDA = 32, Pad1 = 0, TRP = 10, TRFC = 68, Pad2 = 0

--> MC_SEQ_MISC_TIMING2

PA2RDATA = 0, Pad0 = 0, PA2WDATA = 0, Pad1 = 0, FAW = 0, TREDC = 2, TWEDC = 4, T32AW = 0, Pad2 = 0, TWDATATR = 0

--> MC_SEQ_PMG_TIMING

TCKSRE = 2, Pad0 = 0, TCKSRX = 2, Pad1 = 0, TCKE_PULSE = 11, TCKE = 11, SEQ_IDLE = 7, Pad2 = 0, TCKE_PULSE_MSB = 0, SEQ_IDLE_SS = 0

--> MC_ARB_DRAM_TIMING

ACTRD = 16, ACTWR = 12, RASMACTRD = 33, RASMACTWR = 30

--> MC_ARB_DRAM_TIMING2

RAS2RAS = 81, RP = 25, WRPLUSRP = 38, BUS_TURN = 19

--> HEX strap: 77713320000000000839472A50550C0B242045040040040022BB1C005C0B14204A8900A00000012 0100C211E51192613

--> MC_SEQ_WR_CTL_D0

DAT_DLY = 7, DQS_DLY = 7, DQS_XTR = 1, DAT_2Y_DLY = 0, ADR_2Y_DLY = 0, CMD_2Y_DLY = 0, OEN_DLY = 7, OEN_EXT = 3

--> MC_SEQ_WR_CTL_D1

DAT_DLY = 0, DQS_DLY = 0, DQS_XTR = 0, DAT_2Y_DLY = 0, ADR_2Y_DLY = 0, CMD_2Y_DLY = 0, OEN_DLY = 0, OEN_EXT = 0

--> MC_SEQ_RAS_TIMING

TRCDW = 8, TRCDWA = 8, TRCDR = 14, TRCDRA = 14, TRRD = 4, TRC = 42, Pad0 = 0

--> MC_SEQ_CAS_TIMING

TNOPW = 0, TNOPR = 0, TR2W = 21, TCCLD = 2, TR2R = 5, Pad0 = 0, TW2R = 12, TCL = 11, Pad1 = 0

--> MC_SEQ_MISC_TIMING

TRP_WRA = 36, Pad0 = 0, TRP_RDA = 32, Pad1 = 0, TRP = 10, TRFC = 68, Pad2 = 0

--> MC_SEQ_MISC_TIMING2

PA2RDATA = 0, Pad0 = 0, PA2WDATA = 0, Pad1 = 0, FAW = 0, TREDC = 2, TWEDC = 4, T32AW = 0, Pad2 = 0, TWDATATR = 0

--> MC_SEQ_PMG_TIMING

TCKSRE = 2, Pad0 = 0, TCKSRX = 2, Pad1 = 0, TCKE_PULSE = 11, TCKE = 11, SEQ_IDLE = 7, Pad2 = 0, TCKE_PULSE_MSB = 0, SEQ_IDLE_SS = 0

--> MC_ARB_DRAM_TIMING

ACTRD = 16, ACTWR = 12, RASMACTRD = 33, RASMACTWR = 30

--> MC_ARB_DRAM_TIMING2

RAS2RAS = 81, RP = 25, WRPLUSRP = 38, BUS_TURN = 19