Custom RAM Timings for GPU's with GDDR5 - DOWNLOAD LINKS - UPDATED

[niko2004x]

Not same length.
Which one is the real one?

Mine was inherited from linux kernel (at least for R9).
And it seems correct since these registers overflow (https://bitcointalk.org/index.php?topic=1758267.msg18280243#msg18280243)
at least in some official tool for bios generation.
I do not know however if it is ok for bios to overflow these registers.
I collected >100 different timing tables with >800 different timing strings and in all cases high bits of these registers always set to 0.

You can test it (didn't do it myself).
Set high unused bit of TRP/TRP_RDA to 1 and all low to 0 for some high strap.
If card crashes then overflow is not good from bios side too.

[1715237057]

1715237057

[1715237057]

1715237057

[1715237057]

1715237057

[doktor83]

I did not test it, but want to write a tool for myself so that's why im asking

[niko2004x]

I did not test it, but want to write a tool for myself so that's why im asking

If you just need redistributable tool for windows you can try cx_Freeze on my python code.
It will give you one executable file with all libraries bundled-in.

[doktor83]

I did not test it, but want to write a tool for myself so that's why im asking

If you just need redistributable tool for windows you can try cx_Freeze on my python code.
It will give you one executable file with all libraries bundled-in.

Thanks mate, but this way i learn
Cheers

[nerdralph]

nerdralph's goddecode edit :

Code:

typedef struct _SEQ_MISC_TIMING_FORMAT
{
	uint32_t TRP_WRA : 7;
	uint32_t TRP_RDA : 7;
	uint32_t TRP : 6;
	uint32_t TRFC : 9;
	uint32_t Pad0 : 3;
} SEQ_MISC_TIMING_FORMAT;

Niko2004 :

Code:

MC_SEQ_MISC_TIMING_RX=BitStruct("MC_SEQ_MISC_TIMING_RX", #last field is lowest bits
  Bits("unused3", 3), #Unused
  Bits("TRFC", 9),    #Auto-refresh command period - 1
  Bits("unused2", 1), #Unused
  Bits("TRP", 5),     #Precharge command period - 1
  Bits("unused1", 1), #Unused
  Bits("TRP_RDA", 6), #From read with auto-precharge to active - 1
  Bits("TRP_WRA", 7), #From write with auto-precharge to active - 1
)

TRP_RDA
TRP

Not same length.
Which one is the real one?

Mine are correct.   From a chip-design perspective, masking off the "unused" bits would actually add complexity.  The simple, and most logical conclusion is that the fields can store larger values than are required by the specs for currently-produced GDDR5 RAM.  I also suspect if anyone took the time to look at the JEDEC GDDR5 spec, you'd at least see tRP needs to support more than 5 bits (max 31).

To be 100% certain, on my Rx470 (Samsung K4G4) I changed MC_SEQ_MISC_TIMING: 0x09D82033
TRP_WRA=51 TRP_RDA=64 TRP=32 TRFC=157 Pad0=0

With my tweaked strap using 0x09D50CB3 I was getting 29.3Mh/s, and with only the high bit of RP_RDA and RP set, hashrate dropped to 23.1.  I let it run for 15 minutes with those timings and it was stable.

I suspect for GCN1.2 devices (i.e. Tonga) that use the R9 SEQ_MISC format that RP_RDA is actually 7 bits, not 6 plus a 1-bit pad before tRP.

[nerdralph]

I finally got my hands on the JEDEC GDDR5 spec, and am now convinced that there are still some mistakes (or at least mis-naming) in the strap decoding previously discussed.  One thing I noticed a few weeks ago was that tR2R is not mentioned in the Hynix datasheet.  It's not in the JEDEC spec either (which unsurprisingly is the source of much of the Hynix datasheet).  The closest thing I can find is tCCDS and tCCDL.  However if the field labeled tR2R is 5 clocks, then it can't be either CCDS or CCDL, since CCDS is always 2 clocks, and CCDL is either 2 (bank groups disabled) or 3/4 (bank groups enabled).

[nerdralph]

I finally got my hands on the JEDEC GDDR5 spec, and am now convinced that there are still some mistakes (or at least mis-naming) in the strap decoding previously discussed.  One thing I noticed a few weeks ago was that tR2R is not mentioned in the Hynix datasheet.  It's not in the JEDEC spec either (which unsurprisingly is the source of much of the Hynix datasheet).  The closest thing I can find is tCCDS and tCCDL.  However if the field labeled tR2R is 5 clocks, then it can't be either CCDS or CCDL, since CCDS is always 2 clocks, and CCDL is either 2 (bank groups disabled) or 3/4 (bank groups enabled).

No, it's right. TR2R is not mentioned because it's ALWAYS going to be 5 for GDDR5.

OK, so what exactly is it?  If it's not the number of cycles between reads on different banks (since that is tCCD), is it the number of cycles required between 2 reads from the same open page?

[Truthchanter]

Anyway to know which rx gpu models have mem heatsinks? and how much do the heatsinks matter?

[bardacuda]

Anyway to know which rx gpu models have mem heatsinks? and how much do the heatsinks matter?

Try here:

http://www.overclock.net/t/1605802/official-polaris-owners-club/

[nerdralph]

I finally got my hands on the JEDEC GDDR5 spec, and am now convinced that there are still some mistakes (or at least mis-naming) in the strap decoding previously discussed.  One thing I noticed a few weeks ago was that tR2R is not mentioned in the Hynix datasheet.  It's not in the JEDEC spec either (which unsurprisingly is the source of much of the Hynix datasheet).  The closest thing I can find is tCCDS and tCCDL.  However if the field labeled tR2R is 5 clocks, then it can't be either CCDS or CCDL, since CCDS is always 2 clocks, and CCDL is either 2 (bank groups disabled) or 3/4 (bank groups enabled).

No, it's right. TR2R is not mentioned because it's ALWAYS going to be 5 for GDDR5.

OK, so what exactly is it?  If it's not the number of cycles between reads on different banks (since that is tCCD), is it the number of cycles required between 2 reads from the same open page?

I think so, as I know it's calculated from burst length, but I'd have to look up the exact formula again.

My Sapphire Rx470/K4G4 has been running for about a half hour with tR2R=4.  No change in hashrate.  Still at a loss as to what it actually is.

I've also thought more about what tRRD is, and it must be tRRDL.  tRRDS doesn't seem to be in the strap, and is possibly fixed at 4.

[nerdralph]

Anyway to know which rx gpu models have mem heatsinks? and how much do the heatsinks matter?

I'd say active cooling for the RAM makes a 5% difference.  i.e. overclocking to 2100 vs 2000 for 1750-rated RAM.

[christiano88]

Anyway to know which rx gpu models have mem heatsinks? and how much do the heatsinks matter?

Sapphire Nitro/Nitro+/Pulse. MSI Armor+Gaming X/XFX Black+TripleX/Asus Strix I know for sure that they don't. And I can bet that Gigabyte doesn't have either, at least on their regular version (Aorus might have).

[nerdralph]

Anyway to know which rx gpu models have mem heatsinks? and how much do the heatsinks matter?

Sapphire Nitro/Nitro+/Pulse. MSI Armor+Gaming X/XFX Black+TripleX/Asus Strix I know for sure that they don't. And I can bet that Gigabyte doesn't have either, at least on their regular version (Aorus might have).

I saw teardown pictures of a Gigabyte Rx 470 Gaming card that had TIM pads for the memory connected to the main heatsink.  It looked like there was coverage for all 8 RAM chips.

[nerdralph]

My Sapphire Rx470/K4G4 has been running for about a half hour with tR2R=4.  No change in hashrate.  Still at a loss as to what it actually is.

After sleeping on it, I thought maybe tR2R is actually tCCDS.  For GDDR5, tCCDS is always 2, so I tried it with both my Rx 470 cards (Samsung & Hynix).  Both are working fine at 2.
In the past few weeks I've been communicating with some guys at AMD, and found out that they generally won't update the headers (i.e. gmc_8_1_sh_mask.h) unless it is a functional bug.  Apparently there is a lot of BS hoops they have to jump through to in order to publicly release changes.  Since the field wasn't named tCCDS, that could explain why nobody noticed that the memory straps were using 5 instead of 2.

[dallase]

Has anyone looked at the micron straps on the RX 570 yet?

# RX570 Micron
my %straps = (
'2118409','F08C300400050300001E01000000005D070300000000002A0034002F0A04300A00D50A042C0A042 80A04290A042A0A04',
'91645256','0A048B0A045F0A04DD0984DE0984FFFF00204E0001999000000000000022AA1C0060881107C0540 B078F82C000002041',
'3355496','209A8840A100000000030105070C0A100C409C0001999000000000000022AA1C006094120FD0540 C0815449101002041',
'3357483','209A8880A20000000006010A0F190E160D80380101999000000000000022AA1C00A5AC351F10550 E0C21C73203004482',
'3361497','202A8900A5000000000C06141A33182210A0860101777000000000000022AA1C002939572750550 D0FA68803040068C2',
'3363522','20AA8900A6000000000F0A191E401E271248E80101777000000000000022AA1C00AD49593270550 E12AD8A14050068C3',
'3365529','20BA8980A700000000130E202551242E131C190201777000000000000022AA1C00EF516A3790550 F14B20B9505006AE4',
'3357050','20CA89C0A8020000001510232859283315A42C0201777000000000000022AA1C0010D66A3990550 F14344CC505006AE4',
'3357706','20CA8900A902000000161124295C293515F0490201777000000000000022AA1C00315A6B3CA0550 F15B68C1506006AE4',
'3358382','20CA8980A9020000001712262B612B3715C47A0201777000000000000022AA1C0073627C41B0551 016BA0D9606006C06',
'3359385','20EA8940AA030000001914292E692E3B1698AB0201777000000000000022AA1C00B56A7D46C0551 017BE8E1607006C07',
'3360716','20FA8900AB030000001B162C3171313F17400D0301999000000000000022AA1C0018F77E4FD0551 21946501708006C07',
'3363381','20FA8980AC030000001E19323781364718409C0002555000000000000022DD1C0084941212F0540 B0795847102002041',
'3358133','209A8800A00000312006050D0E270F160E80380102777000000000000022DD1C00E7AC352210550 D0A20C7F204002481',
'3361474','209A8800A0000031200C08171B4F172110905F0102777000000000000022DD1C002931462620550 E0BA20793050026A2',
'3362150','20AA8800A0000031200D0A1A1D59192311A0860102777000000000000022DD1C0029B5462930550 E0C244823060026A2',
);

[doktor83]

someone could try them on a 470 card with micron mem

[niko2004x]

Has anyone looked at the micron straps on the RX 570 yet?

# RX570 Micron
my %straps = (
'2118409','F08C300400050300001E01000000005D070300000000002A0034002F0A04300A00D50A042C0A042 80A04290A042A0A04',
'91645256','0A048B0A045F0A04DD0984DE0984FFFF00204E0001999000000000000022AA1C0060881107C0540 B078F82C000002041',
'3355496','209A8840A100000000030105070C0A100C409C0001999000000000000022AA1C006094120FD0540 C0815449101002041',
'3357483','209A8880A20000000006010A0F190E160D80380101999000000000000022AA1C00A5AC351F10550 E0C21C73203004482',
'3361497','202A8900A5000000000C06141A33182210A0860101777000000000000022AA1C002939572750550 D0FA68803040068C2',
'3363522','20AA8900A6000000000F0A191E401E271248E80101777000000000000022AA1C00AD49593270550 E12AD8A14050068C3',
'3365529','20BA8980A700000000130E202551242E131C190201777000000000000022AA1C00EF516A3790550 F14B20B9505006AE4',
'3357050','20CA89C0A8020000001510232859283315A42C0201777000000000000022AA1C0010D66A3990550 F14344CC505006AE4',
'3357706','20CA8900A902000000161124295C293515F0490201777000000000000022AA1C00315A6B3CA0550 F15B68C1506006AE4',
'3358382','20CA8980A9020000001712262B612B3715C47A0201777000000000000022AA1C0073627C41B0551 016BA0D9606006C06',
'3359385','20EA8940AA030000001914292E692E3B1698AB0201777000000000000022AA1C00B56A7D46C0551 017BE8E1607006C07',
'3360716','20FA8900AB030000001B162C3171313F17400D0301999000000000000022AA1C0018F77E4FD0551 21946501708006C07',
'3363381','20FA8980AC030000001E19323781364718409C0002555000000000000022DD1C0084941212F0540 B0795847102002041',
'3358133','209A8800A00000312006050D0E270F160E80380102777000000000000022DD1C00E7AC352210550 D0A20C7F204002481',
'3361474','209A8800A0000031200C08171B4F172110905F0102777000000000000022DD1C002931462620550 E0BA20793050026A2',
'3362150','20AA8800A0000031200D0A1A1D59192311A0860102777000000000000022DD1C0029B5462930550 E0C244823060026A2',
);

Offsets are wrong. 204E0001 is first frequency+type.
Although it is mangled it looks like standard timings for Elpida EDW4032BABG and Hynix H5GC4H24AJR as type 1 and 2.
Nothing interesting.

[niko2004x]

someone could try them on a 470 card with micron mem

Better use random hex string since it will probably give same result. 

[dallase]

Has anyone looked at the micron straps on the RX 570 yet?

# RX570 Micron
my %straps = (
'2118409','F08C300400050300001E01000000005D070300000000002A0034002F0A04300A00D50A042C0A042 80A04290A042A0A04',
'91645256','0A048B0A045F0A04DD0984DE0984FFFF00204E0001999000000000000022AA1C0060881107C0540 B078F82C000002041',
'3355496','209A8840A100000000030105070C0A100C409C0001999000000000000022AA1C006094120FD0540 C0815449101002041',
'3357483','209A8880A20000000006010A0F190E160D80380101999000000000000022AA1C00A5AC351F10550 E0C21C73203004482',
'3361497','202A8900A5000000000C06141A33182210A0860101777000000000000022AA1C002939572750550 D0FA68803040068C2',
'3363522','20AA8900A6000000000F0A191E401E271248E80101777000000000000022AA1C00AD49593270550 E12AD8A14050068C3',
'3365529','20BA8980A700000000130E202551242E131C190201777000000000000022AA1C00EF516A3790550 F14B20B9505006AE4',
'3357050','20CA89C0A8020000001510232859283315A42C0201777000000000000022AA1C0010D66A3990550 F14344CC505006AE4',
'3357706','20CA8900A902000000161124295C293515F0490201777000000000000022AA1C00315A6B3CA0550 F15B68C1506006AE4',
'3358382','20CA8980A9020000001712262B612B3715C47A0201777000000000000022AA1C0073627C41B0551 016BA0D9606006C06',
'3359385','20EA8940AA030000001914292E692E3B1698AB0201777000000000000022AA1C00B56A7D46C0551 017BE8E1607006C07',
'3360716','20FA8900AB030000001B162C3171313F17400D0301999000000000000022AA1C0018F77E4FD0551 21946501708006C07',
'3363381','20FA8980AC030000001E19323781364718409C0002555000000000000022DD1C0084941212F0540 B0795847102002041',
'3358133','209A8800A00000312006050D0E270F160E80380102777000000000000022DD1C00E7AC352210550 D0A20C7F204002481',
'3361474','209A8800A0000031200C08171B4F172110905F0102777000000000000022DD1C002931462620550 E0BA20793050026A2',
'3362150','20AA8800A0000031200D0A1A1D59192311A0860102777000000000000022DD1C0029B5462930550 E0C244823060026A2',
);

Offsets are wrong. 204E0001 is first frequency+type.
Although it is mangled it looks like standard timings for Elpida EDW4032BABG and Hynix H5GC4H24AJR as type 1 and 2.
Nothing interesting.

Is it just Polaris Bios Editor not reading the rom correctly?  Maybe I need to update...

[phobosq]

Just testing Gigabyte RX 570 Gaming, Elpida onboard. First looking - those straps are outrageous - TCL = 23@1750, TRCDR = 26, but at 2000 there are better dragons - TCL = 25, TRCDR = 29, and suddenly TRPWRA = 6. No surprise I got instant freeze with stock bios when set mem clock to 2000.
Trying to optimize it now, but driver signing caught me in 17.4.3, blah.

Polaris Bios Editor works OK, no issues.